I32U Tcc353xInterruptProcess(void) { I32U ret = 0; I08U irqStatus = 0; I32S moduleIndex = 0; I32U totalSize = 0; I08U data = 0x00; /* Read BB Interrupt Status */ Tcc353xApiGetIrqStatus(moduleIndex, &irqStatus); #if defined (_I2C_STS_) totalSize = 0; data = 0x00; /* Tcc353x IRQ Clear */ Tcc353xApiIrqClear(moduleIndex, irqStatus); ret = 0; /* return no data */ #else /* Stream Interrupt */ if (irqStatus&0x01) { TcpalPrintErr((I08S *) "[TCC353X] FIFO overflow[0x%02X] flush!!!\n", irqStatus); /* IRQ Disable - Prevent additional interrupt signal */ data = 0x00; Tcc353xApiRegisterWrite(0,0, 0x03, &data, 1); /* Tcc353x IRQ Clear */ Tcc353xApiIrqClear(moduleIndex, irqStatus); Tcc353xApiInterruptBuffClr(moduleIndex); gOverflowcnt ++; ret = 0; } else { /* Tcc353x IRQ Clear */ Tcc353xApiIrqClear(moduleIndex, irqStatus); Tcc353xApiGetFifoStatus(moduleIndex, &totalSize); ret = totalSize; if(ret>=150*188) TcpalPrintErr((I08S *) "[TCC353X] FIFO stat size[%d]\n", ret); } gDbgIsrCnt++; if(gDbgIsrCnt>100) { gDbgIsrCnt = 0; #ifdef _DBG_CHK_OVERFLOW_CNT_ TcpalPrintStatus((I08S *) "[TCC353X] CurrOverflow Cnt %d\n", gOverflowcnt); #endif } #endif return ret; }
I32U Tcc353xInterruptProcess(void) { I32U ret = 0; I08U irqStatus = 0; I32S moduleIndex = 0; I32U totalSize = 0; /* Read BB Interrupt Status */ Tcc353xApiGetIrqStatus(moduleIndex, &irqStatus); /* Stream Interrupt */ if (irqStatus&0x01) { TcpalPrintErr((I08S *) "[TCC353X] FIFO overflow[0x%02X] flush!!!\n", irqStatus); /* Tcc353x IRQ Clear */ Tcc353xApiIrqClear(moduleIndex, irqStatus); Tcc353xApiInterruptBuffClr(moduleIndex); gOverflowcnt ++; ret = 0; } else { /* Tcc353x IRQ Clear */ Tcc353xApiIrqClear(moduleIndex, irqStatus); Tcc353xApiGetFifoStatus(moduleIndex, &totalSize); ret = totalSize; } gDbgIsrCnt++; if(gDbgIsrCnt>40) { gDbgIsrCnt = 0; #ifdef _DBG_CHK_OVERFLOW_CNT_ TcpalPrintStatus((I08S *) "[TCC353X] CurrOverflow Cnt %d\n", gOverflowcnt); #endif } return ret; }