void low_setRF_Protocol_ISO14443A() { int init_ms; uint8_t fifo_size; uint8_t data_buf[5]; /* Test ISO14443-A/Mifare read UID */ init_ms = Trf797xInitialSettings(); Trf797xReset(); /* Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz)) */ data_buf[0] = MODULATOR_CONTROL; data_buf[1] = 0x31; Trf797xWriteSingle(data_buf, 2); data_buf[0] = MODULATOR_CONTROL; Trf797xReadSingle(data_buf, 1); /* Configure Mode ISO Control Register (0x01) to 0x88 (ISO14443A RX bit rate, 106 kbps) and no RX CRC (CRC is not present in the response)) */ data_buf[0] = ISO_CONTROL; data_buf[1] = 0x88; Trf797xWriteSingle(data_buf, 2); data_buf[0] = ISO_CONTROL; Trf797xReadSingle(data_buf, 1); if(data_buf[0] != 0x88) { // hydraNfcLowLevelException.errorCode = 0x02; // hydraNfcLowLevelException.errorMessage = "low_setRF_Protocol_ISO14443A Error- ISO_CONTROL Error"; // Throw hydraNfcLowLevelException; } /* Turn RF ON (Chip Status Control Register (0x00)) */ Trf797xTurnRfOn(); /* Read back (Chip Status Control Register (0x00) shall be set to RF ON */ data_buf[0] = CHIP_STATE_CONTROL; Trf797xReadSingle(data_buf, 1); return (uint32_t)data_buf[0]; }
static bool hydranfc_test_shield(void) { int init_ms; int err; static uint8_t data_buf[4]; err = 0; /* Software Init TRF7970A */ init_ms = Trf797xInitialSettings(); if (init_ms == TRF7970A_INIT_TIMEOUT) return FALSE; Trf797xReset(); data_buf[0] = CHIP_STATE_CONTROL; Trf797xReadSingle(data_buf, 1); if (data_buf[0] != 0x01) err++; return err == 0; }
void hydranfc_tag_emul_init(void) { uint8_t data_buf[4]; Trf797xInitialSettings(); Trf797xReset(); /* ISO Control */ data_buf[0] = ISO_CONTROL; data_buf[1] = 0x24; /* ISO14443A */ Trf797xWriteSingle(data_buf, 2); /* Configure RX */ data_buf[0] = RX_SPECIAL_SETTINGS; data_buf[1] = 0x3C; Trf797xWriteSingle(data_buf, 2); /* Configure Adjustable FIFO IRQ Levels Register (96B RX & 32B TX) */ data_buf[0] = 0x14; data_buf[1] = 0x0F; Trf797xWriteSingle(data_buf, 2); /* Configure NFC Target Detection Level Register */ /* RF field level required for system wakeup to max */ data_buf[0] = NFC_TARGET_LEVEL; data_buf[1] = NFC_TARGET_LEVEL; data_buf[2] = 0x16; // NFC_LOW_DETECTION data_buf[3] = BIT0; // read the NFCTargetLevel register Trf797xReadSingle(&data_buf[1], 1); data_buf[1] |= BIT2 + BIT1 + BIT0; switch(tag_uid_len) { case 4: data_buf[1] &= ~(BIT7 + BIT6); break; case 7: data_buf[1] &= ~BIT7; data_buf[1] |= BIT6; break; case 10: data_buf[1] &= ~BIT6; data_buf[1] |= BIT7; break; default: break; } data_buf[1] |= BIT5; /* SDD Enabled */ Trf797xWriteSingle(data_buf, 2); data_buf[0] = ISO_14443B_OPTIONS; data_buf[1] = ISO_14443B_OPTIONS; Trf797xReadSingle(&data_buf[1], 1); data_buf[1] |= BIT0; // set 14443A - 4 compliant bit data_buf[2] = CHIP_STATE_CONTROL; data_buf[3] = 0x21; Trf797xWriteSingle(data_buf, 4); /* Configure Test Register */ /* MOD Pin becomes receiver digitized subcarrier output */ /* data_buf[0] = TEST_SETTINGS_1; data_buf[1] = 0x40; Trf797xWriteSingle(data_buf, 2); data_buf[0] = MODULATOR_CONTROL; data_buf[1] = MODULATOR_CONTROL; Trf797xReadSingle(&data_buf[1], 1); data_buf[1] |= BIT3; Trf797xWriteSingle(data_buf, 2); */ write_emul_tag_uid(tag_uid); Trf797xResetIrqStatus(); Trf797xReset(); Trf797xStopDecoders(); Trf797xRunDecoders(); }
void hydranfc_scan_vicinity(t_hydra_console *con) { static uint8_t data_buf[VICINITY_UID_MAX]; uint8_t fifo_size; int i; /* End Test delay */ irq_count = 0; /* Test ISO15693 read UID */ Trf797xInitialSettings(); Trf797xReset(); /* Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz)) */ data_buf[0] = MODULATOR_CONTROL; data_buf[1] = 0x31; Trf797xWriteSingle(data_buf, 2); /* Configure Mode ISO Control Register (0x01) to 0x02 (ISO15693 high bit rate, one subcarrier, 1 out of 4) */ data_buf[0] = ISO_CONTROL; data_buf[1] = 0x02; Trf797xWriteSingle(data_buf, 2); /* Configure Test Settings 1 to BIT6/0x40 => MOD Pin becomes receiver subcarrier output (Digital Output for RX/TX) */ /* data_buf[0] = TEST_SETTINGS_1; data_buf[1] = BIT6; Trf797xWriteSingle(data_buf, 2); data_buf[0] = TEST_SETTINGS_1; Trf797xReadSingle(data_buf, 1); if (data_buf[0] != 0x40) { cprintf(con, "Error Test Settings Register(0x1A) read=0x%02lX (shall be 0x40)\r\n", (uint32_t)data_buf[0]); err++; } */ /* Turn RF ON (Chip Status Control Register (0x00)) */ Trf797xTurnRfOn(); McuDelayMillisecond(10); /* Send Inventory(3B) and receive data + UID */ data_buf[0] = 0x26; /* Request Flags */ data_buf[1] = 0x01; /* Inventory Command */ data_buf[2] = 0x00; /* Mask */ fifo_size = Trf797x_transceive_bytes(data_buf, 3, data_buf, VICINITY_UID_MAX, 10, /* 10ms TX/RX Timeout (shall be less than 10ms (6ms) in High Speed) */ 1); /* CRC enabled */ if (fifo_size > 0) { /* fifo_size should be 10. */ cprintf(con, "UID:"); for (i = 0; i < fifo_size; i++) cprintf(con, " 0x%02lX", (uint32_t)data_buf[i]); cprintf(con, "\r\n"); /* Read RSSI levels and oscillator status(0x0F/0x4F) */ data_buf[0] = RSSI_LEVELS; Trf797xReadSingle(data_buf, 1); if (data_buf[0] < 0x40) { cprintf(con, "RSSI error: 0x%02lX (should be > 0x40)\r\n", (uint32_t)data_buf[0]); } } /* Turn RF OFF (Chip Status Control Register (0x00)) */ Trf797xTurnRfOff(); /* cprintf(con, "irq_count: 0x%02ld\r\n", (uint32_t)irq_count); irq_count = 0; */ }
void hydranfc_scan_mifare(t_hydra_console *con) { uint8_t data_buf[MIFARE_DATA_MAX]; uint8_t atqa_buf[MIFARE_ATQA_MAX]; uint8_t uid_buf[MIFARE_UID_MAX]; uint8_t sak1_buf[MIFARE_SAK_MAX]; uint8_t sak2_buf[MIFARE_SAK_MAX]; uint8_t CL1_buf[MIFARE_CL1_MAX]; uint8_t CL2_buf[MIFARE_CL2_MAX]; uint8_t halt_buf[MIFARE_HALT_MAX]; uint8_t atqa_buf_size = 0; uint8_t uid_buf_size = 0; uint8_t sak1_buf_size = 0; uint8_t sak2_buf_size = 0; uint8_t CL1_buf_size = 0; uint8_t CL2_buf_size = 0; uint8_t halt_buf_size = 0; uint8_t bcc, i; /* End Test delay */ irq_count = 0; /* Test ISO14443-A/Mifare read UID */ Trf797xInitialSettings(); Trf797xReset(); /* * Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK * and default Clock 13.56Mhz)) */ data_buf[0] = MODULATOR_CONTROL; data_buf[1] = 0x31; Trf797xWriteSingle(data_buf, 2); /* * Configure Mode ISO Control Register (0x01) to 0x88 (ISO14443A RX bit * rate, 106 kbps) and no RX CRC (CRC is not present in the response)) */ data_buf[0] = ISO_CONTROL; data_buf[1] = 0x88; Trf797xWriteSingle(data_buf, 2); data_buf[0] = ISO_CONTROL; Trf797xReadSingle(data_buf, 1); if (data_buf[0] != 0x88) cprintf(con, "Error ISO Control Register read=0x%02lX (should be 0x88)\r\n", (uint32_t)data_buf[0]); /* Configure Test Settings 1 to BIT6/0x40 => MOD Pin becomes receiver subcarrier output (Digital Output for RX/TX) */ /* data_buf[0] = TEST_SETTINGS_1; data_buf[1] = BIT6; Trf797xWriteSingle(data_buf, 2); data_buf[0] = TEST_SETTINGS_1; Trf797xReadSingle(data_buf, 1); if (data_buf[0] != 0x40) { cprintf(con, "Error Test Settings Register(0x1A) read=0x%02lX (shall be 0x40)\r\n", (uint32_t)data_buf[0]); err++; } */ /* Turn RF ON (Chip Status Control Register (0x00)) */ Trf797xTurnRfOn(); /* Send REQA (7 bits) and receive ATQA (2 bytes) */ data_buf[0] = 0x26; /* REQA (7bits) */ atqa_buf_size = Trf797x_transceive_bits(data_buf[0], 7, atqa_buf, MIFARE_ATQA_MAX, 10, /* 10ms TX/RX Timeout */ 0); /* TX CRC disabled */ /* Re-send REQA */ if (atqa_buf_size == 0) { /* Send REQA (7 bits) and receive ATQA (2 bytes) */ data_buf[0] = 0x26; /* REQA (7 bits) */ atqa_buf_size = Trf797x_transceive_bits(data_buf[0], 7, atqa_buf, MIFARE_ATQA_MAX, 10, /* 10ms TX/RX Timeout */ 0); /* TX CRC disabled */ } if (atqa_buf_size > 0) { /* Send AntiColl Cascade Level1 (2 bytes) and receive CT+3 UID bytes+BCC (5 bytes) [tag 7 bytes UID] or UID+BCC (5 bytes) [tag 4 bytes UID] */ data_buf[0] = 0x93; data_buf[1] = 0x20; CL1_buf_size = Trf797x_transceive_bytes(data_buf, 2, CL1_buf, MIFARE_CL1_MAX, 10, /* 10ms TX/RX Timeout */ 0); /* TX CRC disabled */ /*Check tag 7 bytes UID*/ if (CL1_buf[0] == 0x88) { uid_buf_size = 7; for (i = 0; i < 3; i++) { uid_buf[i] = CL1_buf[1 + i]; } /* Send AntiColl Cascade Level1 (2 bytes)+CT+3 UID bytes+BCC (5 bytes) and receive SAK1 (1 byte) */ data_buf[0] = 0x93; data_buf[1] = 0x70; for (i = 0; i < CL1_buf_size; i++) { data_buf[2 + i] = CL1_buf[i]; } sak1_buf_size = Trf797x_transceive_bytes(data_buf, (2 + CL1_buf_size), sak1_buf, MIFARE_SAK_MAX, 20, /* 10ms TX/RX Timeout */ 1); /* TX CRC disabled */ if (sak1_buf_size > 0) { /* Send AntiColl Cascade Level2 (2 bytes) and receive 4 UID bytes+BCC (5 bytes)*/ data_buf[0] = 0x95; data_buf[1] = 0x20; CL2_buf_size = Trf797x_transceive_bytes(data_buf, 2, CL2_buf, MIFARE_CL2_MAX, 10, /* 10ms TX/RX Timeout */ 0); /* TX CRC disabled */ if (CL2_buf_size > 0) { for (i = 0; i < 4; i++) { uid_buf[i + 3] = CL2_buf[i]; } data_buf[0] = RSSI_LEVELS; Trf797xReadSingle(data_buf, 1); if (data_buf[0] < 0x40) cprintf(con, "RSSI error: 0x%02lX (should be > 0x40)\r\n", (uint32_t)data_buf[0]); /* * Select RX with CRC_A * Configure Mode ISO Control Register (0x01) to 0x08 * (ISO14443A RX bit rate, 106 kbps) and RX CRC (CRC * is present in the response) */ data_buf[0] = ISO_CONTROL; data_buf[1] = 0x08; Trf797xWriteSingle(data_buf, 2); /* Send AntiColl Cascade Level2 (2 bytes)+4 UID bytes(4 bytes) and receive SAK2 (1 byte) */ data_buf[0] = 0x95; data_buf[1] = 0x70; for (i = 0; i < CL2_buf_size; i++) { data_buf[2 + i] = CL2_buf[i]; } sak2_buf_size = Trf797x_transceive_bytes(data_buf, (2 + CL2_buf_size), sak2_buf, MIFARE_SAK_MAX, 20, /* 10ms TX/RX Timeout */ 1); /* TX CRC disabled */ if (sak2_buf_size > 0) { /* Send Halt(2Bytes+CRC) */ data_buf[0] = 0x50; data_buf[1] = 0x00; halt_buf_size = Trf797x_transceive_bytes(data_buf, 2, halt_buf, MIFARE_HALT_MAX, 5, /* 5ms TX/RX Timeout => shall not receive answer */ 1); /* TX CRC enabled */ } } } } /*tag 4 bytes UID*/ else { uid_buf_size = Trf797x_transceive_bytes(data_buf, 2, uid_buf, MIFARE_UID_MAX, 10, /* 10ms TX/RX Timeout */ 0); /* TX CRC disabled */ if (uid_buf_size > 0) { data_buf[0] = RSSI_LEVELS; Trf797xReadSingle(data_buf, 1); if (data_buf[0] < 0x40) cprintf(con, "RSSI error: 0x%02lX (should be > 0x40)\r\n", (uint32_t)data_buf[0]); /* * Select RX with CRC_A * Configure Mode ISO Control Register (0x01) to 0x08 * (ISO14443A RX bit rate, 106 kbps) and RX CRC (CRC * is present in the response) */ data_buf[0] = ISO_CONTROL; data_buf[1] = 0x08; Trf797xWriteSingle(data_buf, 2); /* Finish Select (6 bytes) and receive SAK1 (1 byte) */ data_buf[0] = 0x93; data_buf[1] = 0x70; for (i = 0; i < uid_buf_size; i++) { data_buf[2 + i] = uid_buf[i]; } sak1_buf_size = Trf797x_transceive_bytes(data_buf, (2 + uid_buf_size), sak1_buf, MIFARE_SAK_MAX, 20, /* 20ms TX/RX Timeout */ 1); /* TX CRC enabled */ if (sak1_buf_size > 0) { /* Send Halt(2Bytes+CRC) */ data_buf[0] = 0x50; data_buf[1] = 0x00; halt_buf_size = Trf797x_transceive_bytes(data_buf, 2, halt_buf, MIFARE_HALT_MAX, 5, /* 5ms TX/RX Timeout => shall not receive answer */ 1); /* TX CRC enabled */ } } } } /* Turn RF OFF (Chip Status Control Register (0x00)) */ Trf797xTurnRfOff(); if(atqa_buf_size > 0) { cprintf(con, "ATQA: "); for (i = 0; i < atqa_buf_size; i++) cprintf(con, " %02X", (uint32_t)atqa_buf[i]); cprintf(con, "\r\n"); } if(sak1_buf_size > 0) { cprintf(con, "SAK1: "); if (sak1_buf_size > 1) sak1_buf_size = 1; for (i = 0; i < sak1_buf_size; i++) cprintf(con, " %02lX", (uint32_t)sak1_buf[i]); cprintf(con, "\r\n"); } if(sak2_buf_size > 0) { cprintf(con, "SAK2: "); for (i = 0; i < sak2_buf_size; i++) cprintf(con, " %02lX", (uint32_t)sak2_buf[i]); cprintf(con, "\r\n"); } if(uid_buf_size > 0) { if(uid_buf_size == 7) { cprintf(con, "UID: "); for (i = 0; i < uid_buf_size ; i++) { cprintf(con, " %02lX", (uint32_t)uid_buf[i]); } cprintf(con, "\r\n"); } else { cprintf(con, "UID: "); bcc = 0; for (i = 0; i < uid_buf_size - 1; i++) { cprintf(con, " %02lX", (uint32_t)uid_buf[i]); bcc ^= uid_buf[i]; } cprintf(con, " (BCC %02lX %s)\r\n", (uint32_t)uid_buf[i], bcc == uid_buf[i] ? "ok" : "NOT OK"); } } if (halt_buf_size > 0) { cprintf(con, "HALT: "); for (i = 0; i < halt_buf_size; i++) cprintf(con, " %02lX", (uint32_t)data_buf[i]); cprintf(con, "\r\n"); } /* cprintf(con, "irq_count: 0x%02ld\r\n", (uint32_t)irq_count); irq_count = 0; */ }