Esempio n. 1
0
//Called at the end of the gesture,
//Returns the id of the recognized gesture or -1 if none.
char input_end(){
  fp_t prob;
  char recognized = -1; // which gesture has been recognized
  fp_t recogprob = -1; // probability of this gesture
  fp_t tmpgesture;
  char i, j;

  started = false;
  for (i = 0; i < 2; i++){
    prob = 0;
    // add probabilities
    for (j = 0; j < 8; j++){
      prob = fp_add(prob, s[j]);
    }
    if (fp_cmp(prob, recogprob)==1) {
      recogprob = prob;
      recognized = i;
    }
  }
  
  //printf("m->prob = %.30f\n", fp2d(recogprob));
  
  UARTSendArray("p=", 2);
  UARTSendInt(recogprob);
  //dir_filter_ref[0] = 0; //reset for next time
  return recognized;
}
Esempio n. 2
0
void hmm() {
  iter++;
  input_reading();
  if(iter == 1000) {
    char out = input_end();
    //UARTSendArray("out=", 4);
    UARTSendInt(out);
    /* UARTSendArray("pass=", 5); */
    /* UARTSendInt(pass); */
    /* pass = 0; */
    iter = 0;
    //__delay_cycles(1000);  // delay 1 ms
  }
}
Esempio n. 3
0
int DDR2Init(void)
{
	int32_t tempVTP;
	
	/* Enable DDR2 module. */
	LPSCTransition(LPSC_DDR2, PD0, PSC_ENABLE);
		
	/* Setup the read latency (CAS Latency + 3 = 6 (but write 6-1=5)) */
	DDR->DDRPHYCR = 0x14001900 | DDR_READ_Latency;

	/* Set TIMUNLOCK bit, CAS Latency, number of banks, page size */
	DDR->SDBCR = 0x00138000 |
		(DDR_NM << 14)   |
		(DDR_CL << 9)    |
		(DDR_IBANK << 4) |
		(DDR_PAGESIZE <<0);
	
	// Program timing registers 
	DDR->SDTIMR = (DDR_T_RFC << 25) |              
		(DDR_T_RP << 22)  |
		(DDR_T_RCD << 19) |
		(DDR_T_WR << 16)  |
		(DDR_T_RAS << 11) |
		(DDR_T_RC << 6)   |
		(DDR_T_RRD << 3)  |
		(DDR_T_WTR << 0);
                  
	DDR->SDTIMR2 = (DDR_T_XSNR << 16) |
		(DDR_T_XSRD << 8)  |
		(DDR_T_RTP << 5)   |
		(DDR_T_CKE << 0);
    
	// Clear the TIMUNLOCK bit 
	DDR->SDBCR &= (~0x00008000);
	
	// Set the refresh rate
	DDR->SDRCR = DDR_RR;
	
	// Dummy write/read to apply timing settings
	DDRMem[0] = DDR_TEST_PATTERN;
	if (DDRMem[0] == DDR_TEST_PATTERN)
		UARTSendInt(DDRMem[0]);
	
	// Set the DDR2 to syncreset
	LPSCTransition(LPSC_DDR2, PD0, PSC_SYNCRESET);

	// Set the DDR2 to enable
	LPSCTransition(LPSC_DDR2, PD0, PSC_ENABLE);
	
			 
	/***************** DDR2 VTP Calibration ****************/
	DDR->VTPIOCR = 0x201F;        // Clear calibration start bit
	DDR->VTPIOCR = 0xA01F;        // Set calibration start bit 
	
	waitloop(11*33);              // Wait for calibration to complete 
		 
	SYSTEM->DDRVTPER = 0x1;       // DDRVTPR Enable register
	
	tempVTP = 0x3FF & DDRVTPR;    // Read calibration data
	
	// Write calibration data to VTP Control register 
	DDR->VTPIOCR = ((DDR->VTPIOCR) & 0xFFFFFC00) | tempVTP; 
	
	// Clear calibration enable bit
	DDR->VTPIOCR = (DDR->VTPIOCR) & (~0x00002000);
	
	// DDRVTPR Enable register - disable DDRVTPR access 
	SYSTEM->DDRVTPER = 0x0;

	return E_PASS;
}
Esempio n. 4
0
void DDR2Init()
{
	Int32 tempVTP;
	
	// Set the DDR2 to enable
	LPSCTransition(LPSC_DDR2, PSC_ENABLE);
		
	// For Micron MT47H64M16BT-37E @ 162 MHz
	// Setup the read latency (CAS Latency + 3 = 6 (but write 6-1=5))
	DDR->DDRPHYCR = (0x50006400) | DDR_READ_Latency;
	// Set TIMUNLOCK bit, CAS LAtency 3, 8 banks, 1024-word page size 
	//DDR->SDBCR = 0x00138632;
	DDR->SDBCR = 0x00138000 |
	             (DDR_NM << 14)   |
	             (DDR_CL << 9)    |
	             (DDR_IBANK << 4) |
	             (DDR_PAGESIZE <<0);
	
	// Program timing registers 
	//DDR->SDTIMR = 0x28923211;
	DDR->SDTIMR = (DDR_T_RFC << 25) |              
                  (DDR_T_RP << 22)  |
                  (DDR_T_RCD << 19) |
                  (DDR_T_WR << 16)  |
                  (DDR_T_RAS << 11) |
                  (DDR_T_RC << 6)   |
                  (DDR_T_RRD << 3)  |
                  (DDR_T_WTR << 0);
                  
	//DDR->SDTIMR2 = 0x0016C722;
	DDR->SDTIMR2 = (DDR_T_XSNR << 16) |
                   (DDR_T_XSRD << 8)  |
                   (DDR_T_RTP << 5)   |
                   (DDR_T_CKE << 0);
    
    
    // Clear the TIMUNLOCK bit 
	DDR->SDBCR &= (~0x00008000);
	
	// Set the refresh rate
	DDR->SDRCR = DDR_RR;
	
	// Dummy write/read to apply timing settings
	DDRMem[0] = DDR_TEST_PATTERN;
	if (DDRMem[0] == DDR_TEST_PATTERN)
          UARTSendInt(DDRMem[0]);
	
	// Set the DDR2 to syncreset
	LPSCTransition(LPSC_DDR2, PSC_SYNCRESET);

	// Set the DDR2 to enable
	LPSCTransition(LPSC_DDR2, PSC_ENABLE);
			 
	/***************** DDR2 VTP Calibration ****************/
	DDR->VTPIOCR = 0x201F;        // Clear calibration start bit
	DDR->VTPIOCR = 0xA01F;        // Set calibration start bit 
	
	waitloop(11*33);              // Wait for calibration to complete 
		 
	SYSTEM->DDRVTPER = 0x1;       // DDRVTPR Enable register
	
	tempVTP = 0x3FF & DDRVTPR;    // Read calibration data
	
	// Write calibration data to VTP Control register 
	DDR->VTPIOCR = ((DDR->VTPIOCR) & 0xFFFFFC00) | tempVTP; 
	
	// Clear calibration enable bit
	DDR->VTPIOCR = (DDR->VTPIOCR) & (~0x00002000);
	
	// DDRVTPR Enable register - disable DDRVTPR access 
	SYSTEM->DDRVTPER = 0x0;
}