void mtk_uart_init (U32 uartclk, U32 baudrate)
{
//#define AP_PERI_GLOBALCON_RST0 (PERI_CON_BASE+0x0)
#define AP_PERI_GLOBALCON_PDN0 (0x10000084)
/* uartclk != 0, means use custom bus clock; uartclk == 0, means use defaul bus clk */
if(0 == uartclk){ // default bus clk
//uartclk = mtk_get_bus_freq()*1000/4;
uartclk = UART_SRC_CLK;
}
mtk_serial_set_current_uart(CFG_UART_META);
//PDN_Power_CONA_DOWN(PDN_PERI_UART1, 0);
//UART_CLR_BITS(1 << 0, AP_PERI_GLOBALCON_RST0); /* Release UART1 reset signal */
//UART_SET_BITS(1 << 24, AP_PERI_GLOBALCON_PDN0); /* Power on UART1 */
//UART_CLR_BITS(1 << 10, AP_PERI_GLOBALCON_PDN0); /* Power on UART1 */
mtk_uart_power_on(CFG_UART_META);
UART_SET_BITS(UART_FCR_FIFO_INIT, UART_FCR(g_uart)); /* clear fifo */
UART_WRITE16(UART_NONE_PARITY | UART_WLS_8 | UART_1_STOP, UART_LCR(g_uart));
serial_setbrg(uartclk, CFG_META_BAUDRATE);
mtk_serial_set_current_uart(CFG_UART_LOG);
//PDN_Power_CONA_DOWN(PDN_PERI_UART4, 0);
//UART_SET_BITS(1 << 12, APMCU_CG_CLR0);
//UART_CLR_BITS(1 << 3, AP_PERI_GLOBALCON_RST0); /* Release UART2 reset signal */
//UART_SET_BITS(1 << 27, AP_PERI_GLOBALCON_PDN0); /* Power on UART2 */
//UART_CLR_BITS(1 << 11, AP_PERI_GLOBALCON_PDN0); /* Power on UART2 */
mtk_uart_power_on(CFG_UART_LOG);
UART_SET_BITS(UART_FCR_FIFO_INIT, UART_FCR(g_uart)); /* clear fifo */
UART_WRITE16(UART_NONE_PARITY | UART_WLS_8 | UART_1_STOP, UART_LCR(g_uart));
serial_setbrg(uartclk, baudrate);
}
__initfunc(static enum uart check_uart(unsigned int iobase))
{
unsigned char b1,b2,b3;
enum uart u;
enum uart uart_tab[] = { c_uart_16450, c_uart_unknown, c_uart_16550, c_uart_16550A };
if (iobase <= 0 || iobase > 0x1000-SER_EXTENT)
return c_uart_unknown;
if (check_region(iobase, SER_EXTENT))
return c_uart_unknown;
b1 = inb(UART_MCR(iobase));
outb(b1 | 0x10, UART_MCR(iobase)); /* loopback mode */
b2 = inb(UART_MSR(iobase));
outb(0x1a, UART_MCR(iobase));
b3 = inb(UART_MSR(iobase)) & 0xf0;
outb(b1, UART_MCR(iobase)); /* restore old values */
outb(b2, UART_MSR(iobase));
if (b3 != 0x90)
return c_uart_unknown;
inb(UART_RBR(iobase));
inb(UART_RBR(iobase));
outb(0x01, UART_FCR(iobase)); /* enable FIFOs */
u = uart_tab[(inb(UART_IIR(iobase)) >> 6) & 3];
if (u == c_uart_16450) {
outb(0x5a, UART_SCR(iobase));
b1 = inb(UART_SCR(iobase));
outb(0xa5, UART_SCR(iobase));
b2 = inb(UART_SCR(iobase));
if ((b1 != 0x5a) || (b2 != 0xa5))
u = c_uart_8250;
}
return u;
}
_init_ (void)
{
unsigned long *src, *dest, *limit;
#ifdef ARM_S3C4530
unsigned long syscfg;
/* Set special register base address to 0x03ff0000. */
syscfg = ARM_SYSCFG_SRBBP_MASK;
/* Set internal SRAM base address. */
syscfg |= ARM_SRAM_BASE >> 10;
/* Cache mode - 4-kbyte SRAM, 4-kbyte cache. */
syscfg |= ARM_SYSCFG_CM_4R_4C;
/* Enable write buffer. */
syscfg |= ARM_SYSCFG_WE;
/* Disable round-robin for DMA-channels. */
syscfg |= ARM_SYSCFG_FP;
ARM_SYSCFG = syscfg;
#ifndef EMULATOR /* not needed on emulator */
/* Invalidate the entire cache.
* Clear 1-kbyte tag memory. */
dest = (unsigned long*) ARM_CACHE_TAG_ADDR;
limit = dest + 1024/4;
while (dest < limit)
*dest++ = 0;
#endif
/* Enable the cache */
syscfg |= ARM_SYSCFG_CE;
ARM_SYSCFG = syscfg;
#endif /* ARM_S3C4530 */
#if defined (ARM_AT91SAM) && !defined (AT91BOOTSTRAP)
/* Enable RESET. */
*AT91C_RSTC_RMR = 0xA5000000 |
(AT91C_RSTC_ERSTL & (4 << 8)) | AT91C_RSTC_URSTEN;
#ifdef AT91C_MC_FMR
/* Flash mode register: set 1 flash wait state and
* a number of master clock cycles in 1.5 microseconds. */
*AT91C_MC_FMR = AT91C_MC_FWS_1FWS |
(AT91C_MC_FMCN & (((KHZ * 3 + 1000) / 2000) << 16));
#endif
/* Disable watchdog. */
*AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS;
/* Main oscillator register: enabling the main oscillator.
* Slow clock is 32768 Hz, or 30.51 usec.
* Start up time = OSCOUNT * 8 / SCK = 1,46 msec.
* Worst case is 15ms, so OSCOUNT = 15 * SCK / 8000 = 61. */
*AT91C_PMC_MOR = AT91C_CKGR_MOSCEN |
(AT91C_CKGR_OSCOUNT & (61 << 8));
while (! (*AT91C_PMC_SR & AT91C_PMC_MOSCS))
continue;
/* PLL register: set multiplier and divider. */
#ifdef AT91C_PMC_PLLR
/* SAM7 development board: we have quartz 18.432 MHz.
* After multiplying by (25+1) and dividing by 5
* we have MCK = 95.8464 MHz.
* PLL startup time estimated at 0.844 msec. */
*AT91C_PMC_PLLR = (AT91C_CKGR_DIV & 0x05) |
(AT91C_CKGR_PLLCOUNT & (28 << 8)) |
(AT91C_CKGR_MUL & (25 << 16));
while (! (*AT91C_PMC_SR & AT91C_PMC_LOCK))
continue;
#else
/* SAM9 development board: quartz 12 MHz.
* Set PLLA to 200 MHz = 12 MHz * (99+1) / 6.
* PLL startup time is 63 slow clocks, or about 2ms. */
*AT91C_PMC_PLLAR = AT91C_CKGR_SRCA |
(AT91C_CKGR_MULA & (99 << 16)) |
AT91C_CKGR_OUTA_2 |
(AT91C_CKGR_PLLACOUNT & (63 << 8)) |
(AT91C_CKGR_DIVA & 6);
while (! (*AT91C_PMC_SR & AT91C_PMC_LOCKA))
continue;
#endif
while (! (*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
continue;
#ifdef ARM_AT91SAM7X256
/* Master clock register: selection of processor clock.
* Use PLL clock divided by 2. */
*AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2;
#endif
#ifdef ARM_AT91SAM9260
/* Set processor clock to PLLA=200MHz.
* For master clock MCK use PLL clock divided by 2. */
*AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;
#endif
while (! (*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
continue;
#ifdef AT91C_PMC_CSS_PLL_CLK
*AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
#else
*AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
#endif
while (! (*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
continue;
#endif /* ARM_AT91SAM && !AT91BOOTSTRAP */
#ifdef ARM_OMAP44XX
extern unsigned _undefined_ [];
extern unsigned _swi_ [];
extern unsigned _prefetch_ [];
extern unsigned _abort_ [];
extern unsigned _irq_ [];
extern unsigned _fiq_ [];
OMAP_UNDEF_EXCEPTION_VECT = (unsigned)_undefined_;
OMAP_SWI_VECT = (unsigned)_swi_;
OMAP_PREFETCH_ABORT_VECT = (unsigned)_prefetch_;
OMAP_DATA_ABORT_VECT = (unsigned)_abort_;
OMAP_IRQ_VECT = (unsigned)_irq_;
OMAP_FIQ_VECT = (unsigned)_fiq_;
ARM_ICCPMR = 0xFF;
#if (KHZ_CLKIN==12000)
CM_SYS_CLKSEL = 1;
#elif (KHZ_CLKIN==16800)
CM_SYS_CLKSEL = 3;
#elif (KHZ_CLKIN==19200)
CM_SYS_CLKSEL = 4;
#elif (KHZ_CLKIN==26000)
CM_SYS_CLKSEL = 5;
#elif (KHZ_CLKIN==38400)
CM_SYS_CLKSEL = 7;
#else
#error Bad KHZ_CLKIN in target.cfg
#endif
/* DPLL_PER (OPP100) recommended settings */
CM_CLKSEL_DPLL_PER = DPLL_DIV(1) | DPLL_MULT(40);
CM_DIV_M2_DPLL_PER = DPLL_CLKx_DIV(8);
CM_DIV_M3_DPLL_PER = DPLL_CLKx_DIV(6);
CM_DIV_M4_DPLL_PER = DPLL_CLKx_DIV(12);
CM_DIV_M5_DPLL_PER = DPLL_CLKx_DIV(9);
CM_DIV_M6_DPLL_PER = DPLL_CLKx_DIV(4);
CM_DIV_M7_DPLL_PER = DPLL_CLKx_DIV(5);
/* DPLL_CORE (OPP100) recommended settings */
CM_CLKSEL_DPLL_CORE = DPLL_DIV(5) | DPLL_MULT(125);
CM_DIV_M2_DPLL_CORE = DPLL_CLKx_DIV(1);
CM_DIV_M3_DPLL_CORE = DPLL_CLKx_DIV(5);
CM_DIV_M4_DPLL_CORE = DPLL_CLKx_DIV(8);
CM_DIV_M5_DPLL_CORE = DPLL_CLKx_DIV(4);
CM_DIV_M6_DPLL_CORE = DPLL_CLKx_DIV(6);
CM_DIV_M7_DPLL_CORE = DPLL_CLKx_DIV(6);
/* DPLL_MPU (OPP100) recommended settings */
CM_CLKSEL_DPLL_MPU = DPLL_DIV(7) | DPLL_MULT(125);
CM_DIV_M2_DPLL_MPU = DPLL_CLKx_DIV(1);
#endif
#ifdef ARM_PANDABOARD
/* Switch off watchdog timer */
*((unsigned *) 0x4A314010) |= 2;
/* Enable clocks for UART3 */
CM_L4PER_UART3_CLKCTRL = MODULEMODE(2);
/* Setting UART3 for debug output */
UART_MDR1(3) = UART_MODE_DISABLE;
/* Set 115200 kbps */
UART_LCR(3) = UART_CONF_MODE_B;
UART_DLL(3) = 0x1A;
UART_DLH(3) = 0x00;
/* Enable FIFOs */
UART_EFR(3) |= UART_EFR_ENHANCED_EN;
UART_LCR(3) = UART_CONF_MODE_A;
UART_MCR(3) |= UART_MCR_TCR_TLR;
UART_FCR(3) |= UART_FCR_FIFO_EN;
UART_MCR(3) &= ~UART_MCR_TCR_TLR;
UART_LCR(3) = UART_CONF_MODE_B;
UART_EFR(3) &= ~UART_EFR_ENHANCED_EN;
/* Set frame format: 8 bit/char, no parity, 1 stop bit */
UART_LCR(3) = UART_LCR_CHAR_LENGTH_8_BIT;
/* Enable UART mode with 16x divisor */
UART_MDR1(3) = UART_MODE_16X;
/* Set pin functions for UART3 */
CONTROL_CORE_PAD0_UART3_RX_IRRX_PAD1_UART3_TX_IRTX = MUXMODE1(0) |
INPUTENABLE1 | MUXMODE2(0) | INPUTENABLE2;
#endif /* ARM_PANDABOARD */
#ifndef EMULATOR /* not needed on emulator */
/* Copy the .data image from flash to ram.
* Linker places it at the end of .text segment. */
src = &_etext;
dest = &__data_start;
limit = &_edata;
while (dest < limit)
*dest++ = *src++;
#endif
/* Initialize .bss segment by zeroes. */
dest = &_edata;
limit = &_end;
while (dest < limit)
*dest++ = 0;
/* Set stack to end of internal SRAM. */
arm_set_stack_pointer ((void*) (ARM_SRAM_BASE + ARM_SRAM_SIZE));
#ifdef ARM_S3C4530
/* Uart 0 for debug output: baud 9600. */
ARM_UCON(0) = ARM_UCON_WL_8 | ARM_UCON_TMODE_IRQ;
ARM_UBRDIV(0) = ((KHZ * 500L / 9600 + 8) / 16 - 1) << 4;
/* On Cronyx board, hardware watchdog is attached to pin P21. */
ARM_IOPCON1 &= ~(1 << 21);
ARM_IOPMOD |= 1 << 21;
/* Global interrupt enable. */
ARM_INTMSK = 0x1fffff;
#endif
#ifdef ARM_AT91SAM
#ifndef AT91BOOTSTRAP
/* Set USART0 for debug output.
* RXD0 and TXD0 lines: disable PIO and assign to A function. */
*AT91C_PIOA_PDR = 3;
*AT91C_PIOA_ASR = 3;
*AT91C_PIOA_BSR = 0;
/* Enable the clock of USART and PIO/ */
*AT91C_PMC_PCER = 1 << AT91C_ID_US0;
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOA;
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
/* Reset receiver and transmitter */
*AT91C_US0_CR = AT91C_US_RSTRX | AT91C_US_RSTTX |
AT91C_US_RXDIS | AT91C_US_TXDIS ;
/* Set baud rate divisor register: baud 115200. */
*AT91C_US0_BRGR = (KHZ * 1000 / 115200 + 8) / 16;
/* Write the Timeguard Register */
*AT91C_US0_TTGR = 0;
/* Set the USART mode */
*AT91C_US0_MR = AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE;
/* Enable the RX and TX PDC transfer requests. */
*AT91C_US0_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN;
/* Enable USART0: RX receiver and TX transmiter. */
*AT91C_US0_CR = AT91C_US_TXEN | AT91C_US_RXEN;
#endif /* !AT91BOOTSTRAP */
#ifdef ARM_AT91SAM9260
/* Use DBGU for debug output.
* PIO and DBGU are already initialized by bootstrap. */
/* Setup exception vectors at address 0. */
{
extern unsigned _start_ [];
unsigned *p;
for (p=0; p<(unsigned*)0x20; ++p) {
*p = 0xe59ff018; /* ldr pc, [pc, #24] */
p[8] = *(unsigned*) ((unsigned) &_start_[8] + (unsigned) p);
}
}
#endif /* ARM_AT91SAM9260 */
/* Setup interrupt vectors. */
{
unsigned i;
for (i=0; i<32; ++i)
AT91C_AIC_SVR[i] = i;
*AT91C_AIC_SPU = 32;
}
/* Disable and clear all interrupts. */
*AT91C_AIC_IDCR = ~0;
*AT91C_AIC_ICCR = ~0;
*AT91C_AIC_EOICR = 0;
#endif /* ARM_AT91SAM */
main ();
}
/*
* UART Init function
*/
void uart_init(uart_num_t uart_num,
uart_databit_t data_nb_bits,
uart_stopbit_t data_nb_stop,
uart_parity_t data_parity,
uint16_t uart_divisor,
uint8_t uart_divaddval,
uint8_t uart_mulval)
{
uint32_t lcr_config;
uint32_t uart_port;
uart_port = uart_num;
switch(uart_num)
{
case UART0_NUM:
/* use PLL1 as clock source for UART0 */
CGU_BASE_UART0_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
break;
case UART1_NUM:
/* use PLL1 as clock source for UART1 */
CGU_BASE_UART1_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
break;
case UART2_NUM:
/* use PLL1 as clock source for UART2 */
CGU_BASE_UART2_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
break;
case UART3_NUM:
/* use PLL1 as clock source for UART3 */
CGU_BASE_UART3_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
break;
default:
return; /* error */
}
/* FIFOs RX/TX Enabled and Reset RX/TX FIFO (DMA Mode is also cleared) */
UART_FCR(uart_port) = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
/* Disable FIFO */
UART_FCR(uart_port) = 0;
// Dummy read (to clear existing data)
while (UART_LSR(uart_port) & UART_LSR_RDR ) {
dummy_read = UART_RBR(uart_port);
}
/* Wait end of TX & disable TX */
UART_TER(uart_port) = UART_TER_TXEN;
/* Wait for current transmit complete */
while (!(UART_LSR(uart_port) & UART_LSR_THRE));
/* Disable Tx */
UART_TER(uart_port) = 0;
/* Disable interrupt */
UART_IER(uart_port) = 0;
/* Set LCR to default state */
UART_LCR(uart_port) = 0;
/* Set ACR to default state */
UART_ACR(uart_port) = 0;
/* Dummy Read to Clear Status */
dummy_read = UART_LSR(uart_port);
/*
Table 835. USART Fractional Divider Register:
UARTbaudrate = PCLK / ( 16* (((256*DLM)+ DLL)*(1+(DivAddVal/MulVal))) )
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1 <= MULVAL <= 15
2. 0 <= DIVADDVAL <= 14
3. DIVADDVAL < MULVAL
*/
/* Set DLAB Bit */
UART_LCR(uart_port) |= UART_LCR_DLAB_EN;
UART_DLM(uart_port) = UART_LOAD_DLM(uart_divisor);
UART_DLL(uart_port) = UART_LOAD_DLL(uart_divisor);
/* Clear DLAB Bit */
UART_LCR(uart_port) &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
UART_FDR(uart_port) = (UART_FDR_MULVAL(uart_mulval) | UART_FDR_DIVADDVAL(uart_divaddval)) & UART_FDR_BITMASK;
/* Read LCR config & Force Enable of Divisor Latches Access */
lcr_config = (UART_LCR(uart_port) & UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
lcr_config |= data_nb_bits; /* Set Nb Data Bits */
lcr_config |= data_nb_stop; /* Set Nb Stop Bits */
lcr_config |= data_parity; /* Set Data Parity */
/* Write LCR (only 8bits) */
UART_LCR(uart_port) = (lcr_config & UART_LCR_BITMASK);
/* Enable TX */
UART_TER(uart_port) = UART_TER_TXEN;
}
