//function definitions
void Clock_init(void)
{
UCS_setExternalClockSource(
32768,
0);
// Set Vcore to accomodate for max. allowed system speed
PMM_setVCore(
PMM_CORE_LEVEL_3
);
// Use 32.768kHz XTAL as reference
UCS_LFXT1Start(
UCS_XT1_DRIVE0,
UCS_XCAP_3
);
// Set system clock to max (25MHz)
UCS_initFLLSettle(
25000,
762
);
SFR_enableInterrupt(
SFR_OSCILLATOR_FAULT_INTERRUPT
);
// Globally enable interrupts
__enable_interrupt();
}
void initClocks(DWORD mclkFreq)
{
// Assign the REFO as the FLL reference clock
UCS_clockSignalInit(
UCS_BASE,
UCS_FLLREF,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
// Assign the REFO as the source for ACLK
UCS_clockSignalInit(
UCS_BASE,
UCS_ACLK,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
UCS_initFLLSettle(
UCS_BASE,
mclkFreq/1000,
mclkFreq/32768);
//use REFO for FLL and ACLK
UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK);
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
}
void USBHAL_initClocks(uint32_t mclkFreq)
{
//setup FLL reference clock
UCS_initClockSignal(UCS_FLLREF, UCS_REFOCLK_SELECT, UCS_CLOCK_DIVIDER_1);
//setup ACLK
UCS_initClockSignal(UCS_ACLK, UCS_REFOCLK_SELECT, UCS_CLOCK_DIVIDER_1);
//sm clock
UCS_initClockSignal(UCS_SMCLK, UCS_DCOCLK_SELECT, UCS_CLOCK_DIVIDER_16);
UCS_initFLLSettle(mclkFreq/1000, mclkFreq/32768);
}
void initClocks(uint32_t mclkFreq)
{
#ifndef DRIVERLIB_LEGACY_MODE
UCS_clockSignalInit(
UCS_FLLREF,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
UCS_clockSignalInit(
UCS_ACLK,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
UCS_initFLLSettle(
mclkFreq/1000,
mclkFreq/32768);
#else
UCS_clockSignalInit(
UCS_BASE,
UCS_FLLREF,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
UCS_clockSignalInit(
UCS_BASE,
UCS_ACLK,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
UCS_initFLLSettle(
UCS_BASE,
mclkFreq/1000,
mclkFreq/32768);
#endif
}
void USBHAL_initClocks(uint32_t mclkFreq)
{
UCS_initClockSignal(
UCS_FLLREF,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
UCS_initClockSignal(
UCS_ACLK,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
UCS_initFLLSettle(
mclkFreq / 1000,
mclkFreq / 32768);
}
void __cc430_mcu_init()
{
// output SMCLK on P.7 for debugging
// PMAPKEYID = 0x2D52; // unlock
// P3MAP7 = PM_SMCLK;
// P3SEL = 0xFF;//(1 << 6);
UCS_clockSignalInit(UCS_FLLREF, UCS_REFOCLK_SELECT, UCS_CLOCK_DIVIDER_1); // set DCO FLL reference = REFO
UCS_clockSignalInit(UCS_ACLK, UCS_REFOCLK_SELECT, UCS_CLOCK_DIVIDER_1); // Set ACLK = REFO
UCS_initFLLSettle(CLOCK_FREQ_MHZ / 1000, (uint16_t) (CLOCK_FREQ_MHZ / REF_FREQ_KHZ)); // blocks until clock settled on requested freq
// uint32_t freq = UCS_getMCLK(); // for verifying
WDTCTL = WDTPW + WDTHOLD; // TODO stop WDT for now
}
void clock_init(void)
{
// UCSCTL1 = DCORSEL_5; // 0x0050
//UCSCTL1 = DCORSEL_1;
// UCSCTL2 = 0x01F9;
// UCSCTL3 = 0x0020;
// UCSCTL4 = 0x0233;
// UCSCTL5 = 0x0040;
// UCSCTL6 = 0x0100;
//Set DCO FLL reference = REFO
UCS_clockSignalInit(
__MSP430_BASEADDRESS_UCS_RF__,
UCS_FLLREF,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
//Set ACLK = REFO
UCS_clockSignalInit(
__MSP430_BASEADDRESS_UCS_RF__,
UCS_ACLK,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
//Set Ratio and Desired MCLK Frequency and initialize DCO
// UCS_initFLLSettle(
// __MSP430_BASEADDRESS_UCS_RF__,
// 1000, // 1000 khz
// 31 // 1000 kHz / 32.768 Khz (Crystal)
// );
_BIS_SR(SCG0); // Disable the FLL control loop
UCS_initFLLSettle(
__MSP430_BASEADDRESS_UCS_RF__,
target_clock_speed_kHz, // 10000 khz
(uint16_t) ((target_clock_speed_kHz * 1000) / 32768) // 10000 kHz / 32.768 Khz = 305(Crystal)
);
_BIC_SR(SCG0); // Enable the FLL control loop
clock_speed = UCS_getSMCLK(__MSP430_BASEADDRESS_UCS_RF__);
//unsigned long clockValueMCLK = UCS_getMCLK(__MSP430_BASEADDRESS_UCS_RF__);
//unsigned long clockValueCLK = UCS_getACLK(__MSP430_BASEADDRESS_UCS_RF__);
}
/* Configures the system clocks:
* MCLK = SMCLK = DCO/FLL = mclkFreq (expected to be expressed in Hz)
* ACLK = FLLref = REFO=32kHz
*
* XT2 is not configured here. Instead, the USB API automatically starts XT2
* when beginning USB communication, and optionally disables it during USB
* suspend. It's left running after the USB host is disconnected, at which
* point you're free to disable it. You need to configure the XT2 frequency
* in the Descriptor Tool (currently set to 4MHz in this example, since that's
* what the Launchpad uses). See the Programmer's Guide for more information.
*/
void InitClock(unsigned long mclkFreq){
UCS_clockSignalInit(
UCS_FLLREF,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
UCS_clockSignalInit(
UCS_ACLK,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1);
UCS_initFLLSettle(
mclkFreq/1000,
mclkFreq/32768);
//use REFO for FLL and ACLK
UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK);
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
}
void clock_init(void)
{
// UCSCTL1 = DCORSEL_5; // 0x0050
//UCSCTL1 = DCORSEL_1;
// UCSCTL2 = 0x01F9;
// UCSCTL3 = 0x0020;
// UCSCTL4 = 0x0233;
// UCSCTL5 = 0x0040;
// UCSCTL6 = 0x0100;
//Set DCO FLL reference = REFO
UCS_clockSignalInit(
__MSP430_BASEADDRESS_UCS_RF__,
UCS_FLLREF,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
//Set ACLK = REFO
UCS_clockSignalInit(
__MSP430_BASEADDRESS_UCS_RF__,
UCS_ACLK,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
//Set Ratio and Desired MCLK Frequency and initialize DCO
// UCS_initFLLSettle(
// __MSP430_BASEADDRESS_UCS_RF__,
// 1000, // 1000 khz
// 31 // 1000 kHz / 32.768 Khz (Crystal)
// );
UCS_initFLLSettle(
__MSP430_BASEADDRESS_UCS_RF__,
10000, // 10000 khz
305 // 10000 kHz / 32.768 Khz (Crystal)
);
clock_speed = UCS_getSMCLK(__MSP430_BASEADDRESS_UCS_RF__);
//unsigned long clockValueMCLK = UCS_getMCLK(__MSP430_BASEADDRESS_UCS_RF__);
//unsigned long clockValueCLK = UCS_getACLK(__MSP430_BASEADDRESS_UCS_RF__);
}
void initClocks()
{
// Set core power mode
PMM_setVCore(PMM_CORE_LEVEL_3);
// Configure pins for crystals
GPIO_setAsPeripheralModuleFunctionInputPin(
GPIO_PORT_P5,
GPIO_PIN4+GPIO_PIN2
);
GPIO_setAsPeripheralModuleFunctionOutputPin(
GPIO_PORT_P5,
GPIO_PIN5+GPIO_PIN3
);
// Inform the system of the crystal frequencies
UCS_setExternalClockSource(
XT1_FREQ, // Frequency of XT1 in Hz.
XT2_FREQ // Frequency of XT2 in Hz.
);
// Initialize the crystals
UCS_turnOnXT2( // used to be UCS_XT2Start in previous driverlib version
UCS_XT2_DRIVE_4MHZ_8MHZ
);
UCS_turnOnLFXT1( //used to be UCS_LFXT1Start in previous driverlib version
UCS_XT1_DRIVE_0,
UCS_XCAP_3
);
UCS_initClockSignal(
UCS_FLLREF, // The reference for Frequency Locked Loop
UCS_XT2CLK_SELECT, // Select XT2
UCS_CLOCK_DIVIDER_4 // The FLL reference will be 1 MHz (4MHz XT2/4)
);
// Start the FLL and let it settle
// This becomes the MCLCK and SMCLK automatically
UCS_initFLLSettle(
MCLK_FREQ_KHZ,
MCLK_FLLREF_RATIO
);
// Optional: set SMCLK to something else than full speed
UCS_initClockSignal(
UCS_SMCLK,
UCS_DCOCLKDIV_SELECT,
UCS_CLOCK_DIVIDER_1
);
// Set auxiliary clock
UCS_initClockSignal(
UCS_ACLK,
UCS_XT1CLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
}
void clock_init(clock_speed_t speed) {
// Turn on XT1 crystal
#ifndef USE_DRIVERLIB
P5SEL |= BIT4;
UCSCTL6 |= XCAP_3; // Internal load cap of 12pF
do { // Wait until XT1 stabilizes
UCSCTL7 &= ~(XT1LFOFFG + DCOFFG); // Clear XT1 fault flag
//
// The DCO fault flag is also cleared,
// since it is supposed to be faulty at startup
// and thus OFIFG will continue to be set unless
// we clear it...
SFRIFG1 &= ~OFIFG; // Clear oscillator fault flag
} while (SFRIFG1 & OFIFG); // Re-test oscillator fault flag
UCSCTL6 &= ~XT1DRIVE_3; // Decrease XT1 drive as it is stabilized
#else
GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P5, GPIO_PIN4);
UCS_turnOnLFXT1(XT1DRIVE_0, UCS_XCAP_3);
#endif
// Set the FLL reference select to XT1 (external 32KHz clock),
// and set the FLL reference divider to 1
#ifndef USE_DRIVERLIB
UCSCTL3 = SELREF__XT1CLK | FLLREFDIV_0;
// Set the MCLK source to DCOCLKDIV
UCSCTL4 = (UCSCTL4 & ~SELM_7) | SELM__DCOCLKDIV;
// Set the SMCLK source to DCOCLKDIV
UCSCTL4 = (UCSCTL4 & ~SELS_7) | SELS__DCOCLKDIV;
#else
UCS_initClockSignal(
UCS_FLLREF,
UCS_XT1CLK_SELECT,
UCS_CLOCK_DIVIDER_1);
#endif
// Initialize the FLL
#ifndef USE_DRIVERLIB
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
uint16_t ratio;
switch (speed) {
case CLKSPEED_16MHZ:
clock_speed = 16000000;
ratio = clock_speed/XT1_FREQ;
UCSCTL1 = DCORSEL_6;
UCSCTL2 = FLLD_1 | (ratio - 1); // FLLD doesn't really matter, since we feed MCLK and SMCLK off DCOCLKDIV and not DCOCLK
break;
case CLKSPEED_1MHZ:
clock_speed = 1000000;
ratio = clock_speed/XT1_FREQ;
UCSCTL1 = DCORSEL_2;
UCSCTL2 = FLLD_1 | (ratio - 1); // FLLD doesn't really matter, since we feed MCLK and SMCLK off DCOCLKDIV and not DCOCLK
break;
}
__bic_SR_register(SCG0); // Enable the FLL control loop
do { // Wait until DCO stabilizes
UCSCTL7 &= ~(DCOFFG); // Clear DCO fault flag
SFRIFG1 &= ~OFIFG; // Clear oscillator fault flag
} while (SFRIFG1 & OFIFG); // Re-test oscillator fault flag
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
while (ratio--)
__delay_cycles(32*32);
#else
switch (speed) {
case CLKSPEED_16MHZ:
clock_speed = 16000000;
break;
case CLKSPEED_1MHZ:
clock_speed = 1000000;
break;
}
UCS_initFLLSettle(clock_speed/1000, clock_speed/XT1_FREQ);
#endif
}
void main (void)
{
//Stop WDT
WDT_hold(__MSP430_BASEADDRESS_WDT_A__);
//Set DCO FLL reference = REFO
UCS_clockSignalInit(
__MSP430_BASEADDRESS_UCS__,
UCS_FLLREF,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
//VLO Clock Sources ACLK
UCS_clockSignalInit(
__MSP430_BASEADDRESS_UCS__,
UCS_ACLK,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
//Set Ratio and Desired MCLK Frequency and initialize DCO
UCS_initFLLSettle(
__MSP430_BASEADDRESS_UCS__,
1048,
32
);
//Setup Port Pins
//P4.0 - P4.7 output
//P4.0 - P4.7 Port Map functions
GPIO_setAsPeripheralModuleFunctionOutputPin(__MSP430_BASEADDRESS_PORT4_R__,
GPIO_PORT_P4,
GPIO_PIN0 + GPIO_PIN1 + GPIO_PIN2 +
GPIO_PIN3 + GPIO_PIN4 + GPIO_PIN5 +
GPIO_PIN6 + GPIO_PIN7 + GPIO_PIN8 +
GPIO_PIN9 + GPIO_PIN10 + GPIO_PIN11 +
GPIO_PIN12 + GPIO_PIN13 + GPIO_PIN14 +
GPIO_PIN15
);
//CONFIGURE PORTS- pass the port_mapping array, start @ P4MAP01, initialize
//a single port, do not allow run-time reconfiguration of port mapping
PMAP_configurePorts(__MSP430_BASEADDRESS_PORT_MAPPING__,
(const unsigned char *)port_mapping,
(unsigned char *)&P4MAP01,
1,
PMAP_DISABLE_RECONFIGURATION
);
//Start Up Down Timer
Timer_startUpDownMode( __MSP430_BASEADDRESS_T0B7__,
TIMER_CLOCKSOURCE_ACLK,
TIMER_CLOCKSOURCE_DIVIDER_1,
256,
TIMER_TAIE_INTERRUPT_DISABLE,
TIMER_CCIE_CCR0_INTERRUPT_DISABLE,
TIMER_SKIP_CLEAR
);
//Generate PWM 1
Timer_initCompare(__MSP430_BASEADDRESS_T0B7__,
TIMER_CAPTURECOMPARE_REGISTER_1,
TIMER_CAPTURECOMPARE_INTERRUPT_DISABLE,
TIMER_OUTPUTMODE_TOGGLE_SET,
192
);
//Generate PWM 2
Timer_initCompare(__MSP430_BASEADDRESS_T0B7__,
TIMER_CAPTURECOMPARE_REGISTER_2,
TIMER_CAPTURECOMPARE_INTERRUPT_DISABLE,
TIMER_OUTPUTMODE_TOGGLE_SET,
128
);
//Generate PWM 3
Timer_initCompare(__MSP430_BASEADDRESS_T0B7__,
TIMER_CAPTURECOMPARE_REGISTER_3,
TIMER_CAPTURECOMPARE_INTERRUPT_DISABLE,
TIMER_OUTPUTMODE_TOGGLE_SET,
96
);
//Generate PWM 4
Timer_initCompare(__MSP430_BASEADDRESS_T0B7__,
TIMER_CAPTURECOMPARE_REGISTER_4,
TIMER_CAPTURECOMPARE_INTERRUPT_DISABLE,
TIMER_OUTPUTMODE_TOGGLE_SET,
64
);
//Generate PWM 5
Timer_initCompare(__MSP430_BASEADDRESS_T0B7__,
TIMER_CAPTURECOMPARE_REGISTER_5,
TIMER_CAPTURECOMPARE_INTERRUPT_DISABLE,
TIMER_OUTPUTMODE_TOGGLE_SET,
32
);
//Generate PWM 6
Timer_initCompare(__MSP430_BASEADDRESS_T0B7__,
TIMER_CAPTURECOMPARE_REGISTER_6,
TIMER_CAPTURECOMPARE_INTERRUPT_DISABLE,
TIMER_OUTPUTMODE_TOGGLE_SET,
16
);
//Enter LPM3
__bis_SR_register(LPM3_bits);
//For debugger
__no_operation();
}
