bool hitTriang(Photon *photon, Triang *triang, const float distance, const Material *materials)
{
Shader shader = DIFFUSE;
// Better idea?
if (fDot(triang->direct, photon->direct) > -EPSILON)
triang->direct = vNeg(triang->direct);
// Update ray's position to the point where the ray hits the sphere
photon->origin = fFMA(photon->direct, distance - UM(10), photon->origin);
photon->lambda = materials[triang->mID].lambda;
if (shader == CRAZY) {
photon->direct = vNorm(vSub(newVec(0.99, 0, 0), photon->origin));
return REFLECTED;
}
else if (shader == SPECULAR) {
// Angle between new and old vector is twice the angle between old vector and normal
Vec reflect = vDot(photon->direct, triang->direct);
photon->direct = vSub(photon->direct, vMul(triang->direct, vAdd(reflect, reflect)));
return REFLECTED;
}
else if (shader == DIFFUSE) {
photon->direct = randDir();
if (fDot(photon->direct, triang->direct) < EPSILON)
photon->direct = vNeg(photon->direct);
return REFLECTED;
}
else return ABSORBED;
}
{ .type = perfctr_um_type_bitmask,
.default_value = 0x1F,
.nvalues = 5 },
{ { 0x10, "Modified (M)" },
{ 0x08, "Owner (O)" },
{ 0x04, "Exclusive (E)" },
{ 0x02, "Shared (S)" },
{ 0x01, "Invalid (I)" } }
};
static const struct perfctr_event k7_official_events[] = {
{ 0x40, 0xF, NULL, "DATA_CACHE_ACCESSES",
"Data cache accesses" },
{ 0x41, 0xF, NULL, "DATA_CACHE_MISSES",
"Data cache misses" },
{ 0x42, 0xF, UM(k7_um_moesi), "DATA_CACHE_REFILLS_FROM_L2",
"Data cache refills from L2" },
{ 0x43, 0xF, UM(k7_um_moesi), "DATA_CACHE_REFILLS_FROM_SYSTEM",
"Data cache refills from system" },
{ 0x44, 0xF, UM(k7_um_moesi), "DATA_CACHE_WRITEBACKS",
"Data cache writebacks" },
{ 0x45, 0xF, NULL, "L1_DTLB_MISSES_AND_L2_DTLB_HITS",
"L1 DTLB misses and L2 DTLB hits" },
{ 0x46, 0xF, NULL, "L1_AND_L2_DTLB_MISSES",
"L1 and L2 DTLB misses" },
{ 0x47, 0xF, NULL, "MISALIGNED_DATA_REFERENCES",
"Misaligned data references" },
{ 0x80, 0xF, NULL, "INSTRUCTION_CACHE_FETCHES",
"Instruction cache fetches" },
{ 0x81, 0xF, NULL, "INSTRUCTION_CACHE_MISSES",
"Instruction cache misses" },
"Number of M lines evicted from the DCU" },
{ 0x48, 0x3, NULL, "DCU_MISS_OUTSTANDING",
"Number of cycles while DCU miss outstanding" },
/* Instruction Fetch Unit (IFU) */
{ 0x80, 0x3, NULL, "IFU_IFETCH",
"Number of non/cachable instruction fetches" }, /* XXX: was IFU_FETCH */
{ 0x81, 0x3, NULL, "IFU_IFETCH_MISS",
"Number of instruction fetch misses" }, /* XXX: was IFU_FETCH_MISS */
{ 0x85, 0x3, NULL, "ITLB_MISS",
"Number of ITLB misses" },
{ 0x86, 0x3, NULL, "IFU_MEM_STALL",
"Cycles instruction fetch pipe is stalled" },
{ 0x87, 0x3, NULL, "ILD_STALL",
"Cycles instruction length decoder is stalled" },
/* L2 Cache */
{ 0x28, 0x3, UM(p6_um_mesi), "L2_IFETCH",
"Number of L2 instruction fetches" },
{ 0x2A, 0x3, UM(p6_um_mesi), "L2_ST",
"Number of L2 data stores" },
{ 0x25, 0x3, NULL, "L2_M_LINES_INM",
"Number of modified lines allocated in L2" },
{ 0x2E, 0x3, UM(p6_um_mesi), "L2_RQSTS",
"Number of L2 requests" },
{ 0x21, 0x3, NULL, "L2_ADS",
"Number of L2 address strobes" },
{ 0x22, 0x3, NULL, "L2_DBUS_BUSY",
"Number of cycles data bus was busy" },
{ 0x23, 0x3, NULL, "L2_DBUS_BUSY_RD",
"Cycles data bus was busy in xfer from L2 to CPU" },
/* External Bus Logic (EBL) */
{ 0x62, 0x3, UM(p6_um_ebl), "BUS_DRDY_CLOCKS",
