void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode) { VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID); VALIDATE_PARAM_PIN(Pin, PORT_SET_PIN_MODE_ID); uint8 port = GET_PIN_PORT(Pin); uint8 pin = GET_PIN_PIN(Pin); uint32 mask = GET_PIN_MASK(Pin); Port_Base[port]->FUN &= ~mask; Port_Base[port]->FUN |= ((Mode & 1) << pin); return; }
void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction ) { VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID); VALIDATE_PARAM_PIN(pin, PORT_SET_PIN_DIRECTION_ID); uint8 port = GET_PIN_PORT(pin); uint32 mask = GET_PIN_MASK(pin); if (direction & PORT_PIN_IN) { Port_Base[port]->DIR |= mask; } else { Port_Base[port]->DIR &= ~mask; } return; }
/** @req SWS_Port_00054 */ void Port_SetPinDirection( Port_PinType bit, Port_PinDirectionType direction ) { VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID); VALIDATE_PARAM_PIN(bit, PORT_SET_PIN_DIRECTION_ID); imask_t state; Irq_Save(state); // Lock interrupts /** @req SWS_Port_00063 */ if (direction==PORT_PIN_IN) { Port_Arc_setPin(bit, Port_Arc_getRegPointerFromPinId( REGISTERSELECTION_PM, bit, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION), 1); Port_Arc_setPin(bit, Port_Arc_getRegPointerFromPinId( REGISTERSELECTION_PIBC, bit, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION), 1); } else { Port_Arc_setPin(bit, Port_Arc_getRegPointerFromPinId( REGISTERSELECTION_PM, bit, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION), 0); Port_Arc_setPin(bit, Port_Arc_getRegPointerFromPinId( REGISTERSELECTION_PIBC, bit, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION), 0); } Irq_Restore(state); // Restore interrupts }
/** @req SWS_Port_00087 PORT_E_MODE_UNCHANGEABLE and PORT_E_PARAM_INVALID_MODE not available */ void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode) { /** @req SWS_Port_00125 */ VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID); VALIDATE_PARAM_PIN(Pin, PORT_SET_PIN_MODE_ID); ArcPort_PinConfig tmpPortCfg = {.flags.UINT16 = Mode}; SET_PORT_REGISTER(Pin, PMC, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PIPC, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PM, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PIBC, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PFC, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PFCE, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PFCAE, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PBDC, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PU, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PD, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PDSC, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PODC, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); SET_PORT_REGISTER(Pin, PIS, tmpPortCfg, PORT_MODULE_ID, PORT_GLOBAL_ID, PORT_E_UNEXPECTED_EXECUTION); }