if (c->post_load) { c->post_load(s); } return 0; } static const VMStateDescription vmstate_gic_irq_state = { .name = "arm_gic_irq_state", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT8(enabled, gic_irq_state), VMSTATE_UINT8(pending, gic_irq_state), VMSTATE_UINT8(active, gic_irq_state), VMSTATE_UINT8(level, gic_irq_state), VMSTATE_BOOL(model, gic_irq_state), VMSTATE_BOOL(edge_trigger, gic_irq_state), VMSTATE_UINT8(group, gic_irq_state), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_gic = { .name = "arm_gic", .version_id = 12, .minimum_version_id = 12, .pre_save = gic_pre_save, .post_load = gic_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32(ctlr, GICState), VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU),
#include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/watchdog/wdt_diag288.h" static WatchdogTimerModel model = { .wdt_name = TYPE_WDT_DIAG288, .wdt_description = "diag288 device for s390x platform", }; static const VMStateDescription vmstate_diag288 = { .name = "vmstate_diag288", .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField[]) { VMSTATE_TIMER_PTR(timer, DIAG288State), VMSTATE_BOOL(enabled, DIAG288State), VMSTATE_END_OF_LIST() } }; static void wdt_diag288_reset(DeviceState *dev) { DIAG288State *diag288 = DIAG288(dev); diag288->enabled = false; timer_del(diag288->timer); } static void diag288_reset(void *opaque) { DeviceState *diag288 = opaque;
mdev = acpi_memory_slot_status(mem_st, dev, errp); if (!mdev) { return; } mdev->is_enabled = false; mdev->dimm = NULL; } static const VMStateDescription vmstate_memhp_sts = { .name = "memory hotplug device state", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_BOOL(is_enabled, MemStatus), VMSTATE_BOOL(is_inserting, MemStatus), VMSTATE_UINT32(ost_event, MemStatus), VMSTATE_UINT32(ost_status, MemStatus), VMSTATE_END_OF_LIST() } }; const VMStateDescription vmstate_memory_hotplug = { .name = "memory hotplug state", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(selector, MemHotplugState), VMSTATE_STRUCT_VARRAY_POINTER_UINT32(devs, MemHotplugState, dev_count,
qemu_log_mask(LOG_GUEST_ERROR, "ipmi:bt: vmstate transfer received bad in value: %d\n", ib->inlen); ib->inlen = 0; } return 0; } const VMStateDescription vmstate_IPMIBT = { .name = TYPE_IPMI_INTERFACE_PREFIX "bt", .version_id = 1, .minimum_version_id = 1, .post_load = ipmi_bt_vmstate_post_load, .fields = (VMStateField[]) { VMSTATE_BOOL(obf_irq_set, IPMIBT), VMSTATE_BOOL(atn_irq_set, IPMIBT), VMSTATE_BOOL(irqs_enabled, IPMIBT), VMSTATE_UINT32(outpos, IPMIBT), VMSTATE_UINT32(outlen, IPMIBT), VMSTATE_UINT8_ARRAY(outmsg, IPMIBT, MAX_IPMI_MSG_SIZE), VMSTATE_UINT32(inlen, IPMIBT), VMSTATE_UINT8_ARRAY(inmsg, IPMIBT, MAX_IPMI_MSG_SIZE), VMSTATE_UINT8(control_reg, IPMIBT), VMSTATE_UINT8(mask_reg, IPMIBT), VMSTATE_UINT8(waiting_rsp, IPMIBT), VMSTATE_UINT8(waiting_seq, IPMIBT), VMSTATE_END_OF_LIST() } };
}, .subsections = (const VMStateDescription*[]) { &vmstate_iplb_extended, NULL } }; static const VMStateDescription vmstate_ipl = { .name = "ipl", .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField[]) { VMSTATE_UINT64(compat_start_addr, S390IPLState), VMSTATE_UINT64(compat_bios_start_addr, S390IPLState), VMSTATE_STRUCT(iplb, S390IPLState, 0, vmstate_iplb, IplParameterBlock), VMSTATE_BOOL(iplb_valid, S390IPLState), VMSTATE_UINT8(cssid, S390IPLState), VMSTATE_UINT8(ssid, S390IPLState), VMSTATE_UINT16(devno, S390IPLState), VMSTATE_END_OF_LIST() } }; static S390IPLState *get_ipl_device(void) { return S390_IPL(object_resolve_path_type("", TYPE_S390_IPL, NULL)); } static uint64_t bios_translate_addr(void *opaque, uint64_t srcaddr) { uint64_t dstaddr = *(uint64_t *) opaque;
BCM2835_IC_ARM_IRQ, ARM_IRQS); sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); sysbus_init_irq(SYS_BUS_DEVICE(s), &s->fiq); } static const VMStateDescription vmstate_bcm2835_ic = { .name = TYPE_BCM2835_IC, .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT64(gpu_irq_level, BCM2835ICState), VMSTATE_UINT64(gpu_irq_enable, BCM2835ICState), VMSTATE_UINT8(arm_irq_level, BCM2835ICState), VMSTATE_UINT8(arm_irq_enable, BCM2835ICState), VMSTATE_BOOL(fiq_enable, BCM2835ICState), VMSTATE_UINT8(fiq_select, BCM2835ICState), VMSTATE_END_OF_LIST() } }; static void bcm2835_ic_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->reset = bcm2835_ic_reset; dc->vmsd = &vmstate_bcm2835_ic; } static TypeInfo bcm2835_ic_info = { .name = TYPE_BCM2835_IC,
if (c->post_load) { c->post_load(s); } return 0; } static const VMStateDescription vmstate_gic_irq_state = { .name = "arm_gic_irq_state", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT8(enabled, gic_irq_state), VMSTATE_UINT8(pending, gic_irq_state), VMSTATE_UINT8(active, gic_irq_state), VMSTATE_UINT8(level, gic_irq_state), VMSTATE_BOOL(model, gic_irq_state), VMSTATE_BOOL(edge_trigger, gic_irq_state), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_gic = { .name = "arm_gic", .version_id = 7, .minimum_version_id = 7, .pre_save = gic_pre_save, .post_load = gic_post_load, .fields = (VMStateField[]) { VMSTATE_BOOL(enabled, GICState), VMSTATE_BOOL_ARRAY(cpu_enabled, GICState, GIC_NCPU), VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
if (errors) { scon->write_errors += errors; } data->header.flags = SCLP_EVENT_BUFFER_ACCEPTED; return SCLP_RC_NORMAL_COMPLETION; } /* functions for live migration */ static const VMStateDescription vmstate_sclplmconsole = { .name = "sclplmconsole", .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField[]) { VMSTATE_BOOL(event.event_pending, SCLPConsoleLM), VMSTATE_UINT32(write_errors, SCLPConsoleLM), VMSTATE_UINT32(length, SCLPConsoleLM), VMSTATE_UINT8_ARRAY(buf, SCLPConsoleLM, SIZE_CONSOLE_BUFFER), VMSTATE_END_OF_LIST() } }; /* qemu object creation and initialization functions */ /* tell character layer our call-back functions */ static int console_init(SCLPEvent *event) { static bool console_available;
VMSTATE_END_OF_LIST() } }; static bool bpbc_needed(void *opaque) { return s390_has_feat(S390_FEAT_BPB); } const VMStateDescription vmstate_bpbc = { .name = "cpu/bpbc", .version_id = 1, .minimum_version_id = 1, .needed = bpbc_needed, .fields = (VMStateField[]) { VMSTATE_BOOL(env.bpbc, S390CPU), VMSTATE_END_OF_LIST() } }; const VMStateDescription vmstate_s390_cpu = { .name = "cpu", .post_load = cpu_post_load, .pre_save = cpu_pre_save, .version_id = 4, .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.regs, S390CPU, 16), VMSTATE_UINT64(env.psw.mask, S390CPU), VMSTATE_UINT64(env.psw.addr, S390CPU), VMSTATE_UINT64(env.psa, S390CPU),
static const MemoryRegionOps bcm2835_property_ops = { .read = bcm2835_property_read, .write = bcm2835_property_write, .endianness = DEVICE_NATIVE_ENDIAN, .valid.min_access_size = 4, .valid.max_access_size = 4, }; static const VMStateDescription vmstate_bcm2835_property = { .name = TYPE_BCM2835_PROPERTY, .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_MACADDR(macaddr, BCM2835PropertyState), VMSTATE_UINT32(addr, BCM2835PropertyState), VMSTATE_BOOL(pending, BCM2835PropertyState), VMSTATE_END_OF_LIST() } }; static void bcm2835_property_init(Object *obj) { BCM2835PropertyState *s = BCM2835_PROPERTY(obj); memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_property_ops, s, TYPE_BCM2835_PROPERTY, 0x10); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(s), &s->mbox_irq); } static void bcm2835_property_reset(DeviceState *dev)
} return; } static WatchdogTimerModel model = { .wdt_name = TYPE_ASPEED_WDT, .wdt_description = "aspeed watchdog device", }; static const VMStateDescription vmstate_aspeed_wdt = { .name = "vmstate_aspeed_wdt", .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField[]) { VMSTATE_TIMER_PTR(timer, AspeedWDTState), VMSTATE_BOOL(enabled, AspeedWDTState), VMSTATE_END_OF_LIST() } }; static const MemoryRegionOps aspeed_wdt_ops = { .read = aspeed_wdt_read, .write = aspeed_wdt_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid.min_access_size = 4, .valid.max_access_size = 4, .valid.unaligned = false, }; static void aspeed_wdt_reset(DeviceState *dev) {
s->busses[i] = i2c_init_bus(DEVICE(s), bus_name); } } static void pca954x_realize(DeviceState *dev, Error **errp) { /* Dummy */ } static const VMStateDescription vmstate_PCA954X = { .name = "pca954x", .version_id = 1, .fields = (VMStateField[]) { VMSTATE_I2C_SLAVE(i2c, PCA954XState), VMSTATE_UINT8(control_reg, PCA954XState), VMSTATE_BOOL(control_decoded, PCA954XState), VMSTATE_UINT8(active_lanes, PCA954XState), VMSTATE_UINT8(lanes, PCA954XState), VMSTATE_BOOL(mux, PCA954XState), VMSTATE_END_OF_LIST() } }; static Property pca954x_properties[] = { /* These could be GPIOs, but the application is rare, just let machine model * tie them with props */ DEFINE_PROP_UINT8("chip-enable", PCA954XState, chip_enable, 0), DEFINE_PROP_END_OF_LIST(), };
cdev = get_cpu_status(cpu_st, dev); if (!cdev) { return; } cdev->cpu = NULL; } static const VMStateDescription vmstate_cpuhp_sts = { .name = "CPU hotplug device state", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_BOOL(is_inserting, AcpiCpuStatus), VMSTATE_BOOL(is_removing, AcpiCpuStatus), VMSTATE_UINT32(ost_event, AcpiCpuStatus), VMSTATE_UINT32(ost_status, AcpiCpuStatus), VMSTATE_END_OF_LIST() } }; const VMStateDescription vmstate_cpu_hotplug = { .name = "CPU hotplug state", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(selector, CPUHotplugState), VMSTATE_UINT8(command, CPUHotplugState),
* timeout value is currently ignored by Linux, anyway */ sq->timeout = cpu_to_be16(0); sq->unit = cpu_to_be16(0); *slen -= sizeof(SignalQuiesce); return 1; } static const VMStateDescription vmstate_sclpquiesce = { .name = "sclpquiesce", .version_id = 0, .minimum_version_id = 0, .minimum_version_id_old = 0, .fields = (VMStateField[]) { VMSTATE_BOOL(event_pending, SCLPEvent), VMSTATE_END_OF_LIST() } }; typedef struct QuiesceNotifier QuiesceNotifier; static struct QuiesceNotifier { Notifier notifier; SCLPEvent *event; } qn; static void quiesce_powerdown_req(Notifier *n, void *opaque) { QuiesceNotifier *qn = container_of(n, QuiesceNotifier, notifier); SCLPEvent *event = qn->event;
ibe->waiting_rsp = false; ibe->inbuf[1] = ibe->outbuf[1] | 0x04; ibe->inbuf[2] = ibe->outbuf[2]; ibe->inbuf[3] = IPMI_CC_BMC_INIT_IN_PROGRESS; iic->handle_rsp(ii, ibe->outbuf[0], ibe->inbuf + 1, 3); } return 0; } static const VMStateDescription vmstate_ipmi_bmc_extern = { .name = TYPE_IPMI_BMC_EXTERN, .version_id = 1, .minimum_version_id = 1, .post_load = ipmi_bmc_extern_post_migrate, .fields = (VMStateField[]) { VMSTATE_BOOL(send_reset, IPMIBmcExtern), VMSTATE_BOOL(waiting_rsp, IPMIBmcExtern), VMSTATE_END_OF_LIST() } }; static void ipmi_bmc_extern_init(Object *obj) { IPMIBmcExtern *ibe = IPMI_BMC_EXTERN(obj); ibe->extern_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, extern_timeout, ibe); vmstate_register(NULL, 0, &vmstate_ipmi_bmc_extern, ibe); } static Property ipmi_bmc_extern_properties[] = { DEFINE_PROP_CHR("chardev", IPMIBmcExtern, chr),
.endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_imx_gpio = { .name = TYPE_IMX_GPIO, .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(dr, IMXGPIOState), VMSTATE_UINT32(gdir, IMXGPIOState), VMSTATE_UINT32(psr, IMXGPIOState), VMSTATE_UINT64(icr, IMXGPIOState), VMSTATE_UINT32(imr, IMXGPIOState), VMSTATE_UINT32(isr, IMXGPIOState), VMSTATE_BOOL(has_edge_sel, IMXGPIOState), VMSTATE_UINT32(edge_sel, IMXGPIOState), VMSTATE_END_OF_LIST() } }; static Property imx_gpio_properties[] = { DEFINE_PROP_BOOL("has-edge-sel", IMXGPIOState, has_edge_sel, true), DEFINE_PROP_END_OF_LIST(), }; static void imx_gpio_reset(DeviceState *dev) { IMXGPIOState *s = IMX_GPIO(dev); s->dr = 0;
if (iib->isairq > 0) { isa_init_irq(isadev, &iib->bt.irq, iib->isairq); iib->bt.use_irq = 1; } qdev_set_legacy_instance_id(dev, iib->bt.io_base, iib->bt.io_length); isa_register_ioport(isadev, &iib->bt.io, iib->bt.io_base); } static const VMStateDescription vmstate_ISAIPMIBTDevice = { .name = TYPE_IPMI_INTERFACE, .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_BOOL(bt.obf_irq_set, ISAIPMIBTDevice), VMSTATE_BOOL(bt.atn_irq_set, ISAIPMIBTDevice), VMSTATE_BOOL(bt.use_irq, ISAIPMIBTDevice), VMSTATE_BOOL(bt.irqs_enabled, ISAIPMIBTDevice), VMSTATE_UINT32(bt.outpos, ISAIPMIBTDevice), VMSTATE_VBUFFER_UINT32(bt.outmsg, ISAIPMIBTDevice, 1, NULL, 0, bt.outlen), VMSTATE_VBUFFER_UINT32(bt.inmsg, ISAIPMIBTDevice, 1, NULL, 0, bt.inlen), VMSTATE_UINT8(bt.control_reg, ISAIPMIBTDevice), VMSTATE_UINT8(bt.mask_reg, ISAIPMIBTDevice), VMSTATE_UINT8(bt.waiting_rsp, ISAIPMIBTDevice), VMSTATE_UINT8(bt.waiting_seq, ISAIPMIBTDevice), VMSTATE_END_OF_LIST() } };
}; static const VMStateDescription vmstate_m25p80 = { .name = "m25p80", .version_id = 0, .minimum_version_id = 0, .pre_save = m25p80_pre_save, .fields = (VMStateField[]) { VMSTATE_UINT8(state, Flash), VMSTATE_UINT8_ARRAY(data, Flash, 16), VMSTATE_UINT32(len, Flash), VMSTATE_UINT32(pos, Flash), VMSTATE_UINT8(needed_bytes, Flash), VMSTATE_UINT8(cmd_in_progress, Flash), VMSTATE_UINT32(cur_addr, Flash), VMSTATE_BOOL(write_enable, Flash), VMSTATE_BOOL(reset_enable, Flash), VMSTATE_UINT8(ear, Flash), VMSTATE_BOOL(four_bytes_address_mode, Flash), VMSTATE_UINT32(nonvolatile_cfg, Flash), VMSTATE_UINT32(volatile_cfg, Flash), VMSTATE_UINT32(enh_volatile_cfg, Flash), VMSTATE_BOOL(quad_enable, Flash), VMSTATE_UINT8(spansion_cr1nv, Flash), VMSTATE_UINT8(spansion_cr2nv, Flash), VMSTATE_UINT8(spansion_cr3nv, Flash), VMSTATE_UINT8(spansion_cr4nv, Flash), VMSTATE_END_OF_LIST() } };
.fields = (VMStateField[]) { VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(rx_pool, VIOsPAPRVLANDevice, RX_MAX_POOLS, 1, vmstate_rx_buffer_pool, RxBufPool), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_spapr_llan = { .name = "spapr_llan", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_SPAPR_VIO(sdev, VIOsPAPRVLANDevice), /* LLAN state */ VMSTATE_BOOL(isopen, VIOsPAPRVLANDevice), VMSTATE_UINT64(buf_list, VIOsPAPRVLANDevice), VMSTATE_UINT32(add_buf_ptr, VIOsPAPRVLANDevice), VMSTATE_UINT32(use_buf_ptr, VIOsPAPRVLANDevice), VMSTATE_UINT32(rx_bufs, VIOsPAPRVLANDevice), VMSTATE_UINT64(rxq_ptr, VIOsPAPRVLANDevice), VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription * []) { &vmstate_rx_pools, NULL } }; static void spapr_vlan_class_init(ObjectClass *klass, void *data)
} static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob, const char *name, uint64_t max_size) { return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, name, virt_acpi_build_update, build_state); } static const VMStateDescription vmstate_virt_acpi_build = { .name = "virt_acpi_build", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_BOOL(patched, AcpiBuildState), VMSTATE_END_OF_LIST() }, }; void virt_acpi_setup(VirtGuestInfo *guest_info) { AcpiBuildTables tables; AcpiBuildState *build_state; if (!guest_info->fw_cfg) { trace_virt_acpi_setup(); return; } if (!acpi_enabled) {
size = memory_region_size(port->downstream); memory_region_init_io(&port->upstream, obj, &tz_ppc_ops, port, name, size); sysbus_init_mmio(sbd, &port->upstream); g_free(name); } } static const VMStateDescription tz_ppc_vmstate = { .name = "tz-ppc", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16), VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16), VMSTATE_BOOL(cfg_sec_resp, TZPPC), VMSTATE_BOOL(irq_enable, TZPPC), VMSTATE_BOOL(irq_clear, TZPPC), VMSTATE_BOOL(irq_status, TZPPC), VMSTATE_END_OF_LIST() } }; #define DEFINE_PORT(N) \ DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \ TYPE_MEMORY_REGION, MemoryRegion *) static Property tz_ppc_properties[] = { DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0), DEFINE_PORT(0), DEFINE_PORT(1),