static bool test_no_msix(void *opaque, int version_id) { return !test_msix(opaque, version_id); } static const VMStateDescription ivshmem_vmsd = { .name = "ivshmem", .version_id = 1, .minimum_version_id = 1, .pre_load = ivshmem_pre_load, .post_load = ivshmem_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix), VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix), VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix), VMSTATE_END_OF_LIST() }, .load_state_old = ivshmem_load_old, .minimum_version_id_old = 0 }; static Property ivshmem_properties[] = { DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), DEFINE_PROP_STRING("size", IVShmemState, sizearg), DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, false), DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true),
/* Reservation */ VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), /* Supervisor mode architected state */ VMSTATE_UINTTL(env.msr, PowerPCCPU), /* Internal state */ VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), /* FIXME: access_type? */ /* Sanity checking */ VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, cpu_pre_2_8_migration), VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription*[]) { &vmstate_fpu, &vmstate_altivec, &vmstate_vsx, &vmstate_sr, #ifdef TARGET_PPC64 &vmstate_tm, &vmstate_slb, #endif /* TARGET_PPC64 */ &vmstate_tlb6xx, &vmstate_tlbemb, &vmstate_tlbmas, &vmstate_compat,