static DECLFW(Mapper65_write) { //if(A>=0x9000 && A<=0x9006) // printf("$%04x:$%02x, %d\n",A,V,scanline); switch(A) { //default: printf("$%04x:$%02x\n",A,V); // break; case 0x8000:ROM_BANK8(0x8000,V);break; // case 0x9000:printf("$%04x:$%02x\n",A,V);MIRROR_SET2((V>>6)&1);break; case 0x9001:MIRROR_SET(V>>7);break; case 0x9003:IRQa=V&0x80;X6502_IRQEnd(FCEU_IQEXT);break; case 0x9004:IRQCount=IRQLatch;break; case 0x9005: IRQLatch&=0x00FF; IRQLatch|=V<<8; break; case 0x9006: IRQLatch&=0xFF00;IRQLatch|=V; break; case 0xB000:VROM_BANK1(0x0000,V);break; case 0xB001:VROM_BANK1(0x0400,V);break; case 0xB002:VROM_BANK1(0x0800,V);break; case 0xB003:VROM_BANK1(0x0C00,V);break; case 0xB004:VROM_BANK1(0x1000,V);break; case 0xB005:VROM_BANK1(0x1400,V);break; case 0xB006:VROM_BANK1(0x1800,V);break; case 0xB007:VROM_BANK1(0x1C00,V);break; case 0xa000:ROM_BANK8(0xA000,V);break; case 0xC000:ROM_BANK8(0xC000,V);break; } //MIRROR_SET2(1); }
static DECLFW(Mapper16_write) { A&=0xF; if(A<=0x7) VROM_BANK1(A<<10,V); else if(A==0x8) ROM_BANK16(0x8000,V); else switch(A) { case 0x9: switch(V&3) { case 0x00:MIRROR_SET2(1);break; case 0x01:MIRROR_SET2(0);break; case 0x02:onemir(0);break; case 0x03:onemir(1);break; } break; case 0xA:X6502_IRQEnd(FCEU_IQEXT); IRQa=V&1; IRQCount=IRQLatch; break; case 0xB:IRQLatch&=0xFF00; IRQLatch|=V; break; case 0xC:IRQLatch&=0xFF; IRQLatch|=V<<8; break; case 0xD: break;/* Serial EEPROM control port */ } }
static DECLFW(Mapper23_write) { if((A&0xF000)==0x8000) { if(K4sel&2) ROM_BANK8(0xC000,V); else ROM_BANK8(0x8000,V); } else if((A&0xF000)==0xA000) ROM_BANK8(0xA000,V); else { A|=((A>>2)&0x3)|((A>>4)&0x3)|((A>>6)&0x3); A&=0xF003; if(A>=0xb000 && A<=0xe003) { int x=((A>>1)&1)|((A-0xB000)>>11); K4buf[x]&=(0xF0)>>((A&1)<<2); K4buf[x]|=(V&0xF)<<((A&1)<<2); VROM_BANK1(x<<10,K4buf[x]); } else switch(A)
static DECLFW(Mapper27_write) { int regnum; A&=0xF00F; if((A>=0xB000) && (A<=0xE003)) { regnum=((((A>>12)+1)&0x03)<<1)|((A&0x02)>>1); if(A&1) regchr[regnum]=(regchr[regnum]&0x00F)|(V<<4); else regchr[regnum]=(regchr[regnum]&0x1F0)|(V&0xF); VROM_BANK1(regnum<<10,regchr[regnum]); }
static DECLFW(Mapper24_write) { if(swaparoo) A=(A&0xFFFC)|((A>>1)&1)|((A<<1)&2); if(A>=0x9000 && A<=0xb002) { VRC6SW(A,V); return; } A&=0xF003; // if(A>=0xF000) printf("%d, %d, $%04x:$%02x\n",scanline,timestamp,A,V); switch(A&0xF003) { case 0x8000:ROM_BANK16(0x8000,V);break; case 0xB003: switch(V&0xF) { case 0x0:MIRROR_SET2(1);break; case 0x4:MIRROR_SET2(0);break; case 0x8:onemir(0);break; case 0xC:onemir(1);break; } break; case 0xC000:ROM_BANK8(0xC000,V);break; case 0xD000:VROM_BANK1(0x0000,V);break; case 0xD001:VROM_BANK1(0x0400,V);break; case 0xD002:VROM_BANK1(0x0800,V);break; case 0xD003:VROM_BANK1(0x0c00,V);break; case 0xE000:VROM_BANK1(0x1000,V);break; case 0xE001:VROM_BANK1(0x1400,V);break; case 0xE002:VROM_BANK1(0x1800,V);break; case 0xE003:VROM_BANK1(0x1c00,V);break; case 0xF000:IRQLatch=V; //acount=0; break; case 0xF001:IRQa=V&2; vrctemp=V&1; if(V&2) { IRQCount=IRQLatch; acount=0; } X6502_IRQEnd(FCEU_IQEXT); break; case 0xf002:IRQa=vrctemp; X6502_IRQEnd(FCEU_IQEXT);break; case 0xF003:break; } }
static void m83chr(void) { // if(0) // { // VROM_BANK2(0x0000,mapbyte2[0]); // VROM_BANK2(0x0800,mapbyte2[1]); // VROM_BANK2(0x1000,mapbyte2[6]); // VROM_BANK2(0x1800,mapbyte2[7]); // } // else // { int x; for(x=0; x<8; x++) VROM_BANK1(x*0x400,mapbyte2[x]|((mapbyte1[0]&0x30)<<4)); // } }
static DECLFW(Mapper33_write) { //printf("%04x:%02x, %d\n",A,V,scanline); A&=0xF003; if(A>=0xA000 && A<=0xA003) VROM_BANK1(0x1000+((A&3)<<10),V); else switch(A) { case 0x8000:if(!is48) MIRROR_SET((V>>6)&1); ROM_BANK8(0x8000,V); break; case 0x8001:ROM_BANK8(0xA000,V); break; case 0x8002:VROM_BANK2(0x0000,V);break; case 0x8003:VROM_BANK2(0x0800,V);break; } }
static DECLFW(Mapper69_write) { switch(A&0xE000) { case 0x8000:sunselect=V;break; case 0xa000: sunselect&=0xF; if(sunselect<=7) VROM_BANK1(sunselect<<10,V); else switch(sunselect&0x0f) { case 8: sungah=V; if(V&0x40) { if(V&0x80) // Select WRAM setprg8r(0x10,0x6000,0); } else setprg8(0x6000,V); break; case 9:ROM_BANK8(0x8000,V);break; case 0xa:ROM_BANK8(0xa000,V);break; case 0xb:ROM_BANK8(0xc000,V);break; case 0xc: switch(V&3) { case 0:MIRROR_SET2(1);break; case 1:MIRROR_SET2(0);break; case 2:onemir(0);break; case 3:onemir(1);break; } break; case 0xd:IRQa=V;X6502_IRQEnd(FCEU_IQEXT);break; case 0xe:IRQCount&=0xFF00;IRQCount|=V;X6502_IRQEnd(FCEU_IQEXT);break; case 0xf:IRQCount&=0x00FF;IRQCount|=V<<8;X6502_IRQEnd(FCEU_IQEXT);break; } break; } }
static DECLFW(Mapper32_write) { switch(A>>12) { case 0x8: mapbyte1[1]=V; if(IREMCon) {ROM_BANK8(0xc000,V);ROM_BANK8(0x8000,~1);} else {ROM_BANK8(0x8000,V);ROM_BANK8(0xc000,~1);} break; case 0x9:IREMCon=(V>>1)&1; if(IREMCon) {ROM_BANK8(0xc000,mapbyte1[1]);ROM_BANK8(0x8000,~1);} else {ROM_BANK8(0x8000,mapbyte1[1]); ROM_BANK8(0xc000,~1);} MIRROR_SET(V&1); break; case 0xa:ROM_BANK8(0xA000,V); break; } if((A&0xF000)==0xb000) VROM_BANK1((A&0x7)<<10,V); }