static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl) { u32 reg_val = readl(&disp_ctrl->cmd.state_access); writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt); /* Enable DC now - otherwise pure text console may not show. */ writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd); writel(reg_val, &disp_ctrl->cmd.state_access); }
static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor) { struct tegra_dc *dc = sor->dc; struct display_controller *disp_ctrl = (void *)dc->base; u32 reg_val = READL(&disp_ctrl->cmd.state_access); WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); WRITEL(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt); /* Enable DC now - otherwise pure text console may not show. */ WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); WRITEL(reg_val, &disp_ctrl->cmd.state_access); }