void Cnf_AddCardinConstrTest()
{
int i, status, nVars = 7;
Vec_Int_t * vVars = Vec_IntStartNatural( nVars );
sat_solver * pSat = sat_solver_new();
sat_solver_setnvars( pSat, nVars );
Cnf_AddCardinConstr( pSat, vVars );
while ( 1 )
{
status = sat_solver_solve( pSat, NULL, NULL, 0, 0, 0, 0 );
if ( status != l_True )
break;
Vec_IntClear( vVars );
for ( i = 0; i < nVars; i++ )
{
Vec_IntPush( vVars, Abc_Var2Lit(i, sat_solver_var_value(pSat, i)) );
printf( "%d", sat_solver_var_value(pSat, i) );
}
printf( "\n" );
status = sat_solver_addclause( pSat, Vec_IntArray(vVars), Vec_IntArray(vVars) + Vec_IntSize(vVars) );
if ( status == 0 )
break;
}
sat_solver_delete( pSat );
Vec_IntFree( vVars );
}
/**Function*************************************************************
Synopsis [Convert TT to GIA via DSD.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Dsm_ManTruthToGia( void * p, word * pTruth, Vec_Int_t * vLeaves, Vec_Int_t * vCover )
{
int fUseMuxes = 0;
int fDelayBalance = 1;
Gia_Man_t * pGia = (Gia_Man_t *)p;
int nSizeNonDec;
char pDsd[1000];
m_Calls++;
assert( Vec_IntSize(vLeaves) <= DAU_DSD_MAX_VAR );
// collect delay information
if ( fDelayBalance && fUseMuxes )
{
int i, iLit, pVarLevels[DAU_DSD_MAX_VAR];
Vec_IntForEachEntry( vLeaves, iLit, i )
pVarLevels[i] = Gia_ObjLevelId( pGia, Abc_Lit2Var(iLit) );
nSizeNonDec = Dau_DsdDecomposeLevel( pTruth, Vec_IntSize(vLeaves), fUseMuxes, 1, pDsd, pVarLevels );
}
else
nSizeNonDec = Dau_DsdDecompose( pTruth, Vec_IntSize(vLeaves), fUseMuxes, 1, pDsd );
if ( nSizeNonDec )
m_NonDsd++;
// printf( "%s\n", pDsd );
if ( fDelayBalance )
return Dau_DsdToGia( pGia, pDsd, Vec_IntArray(vLeaves), vCover );
else
return Dau_DsdToGia2( pGia, pDsd, Vec_IntArray(vLeaves), vCover );
}
/**Function*************************************************************
Synopsis [Checks if the clause holds using BMC.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fra_ClauCheckBmc( Cla_Man_t * p, Vec_Int_t * vClause )
{
int nBTLimit = 0;
int RetValue;
RetValue = sat_solver_solve( p->pSatBmc, Vec_IntArray(vClause), Vec_IntArray(vClause) + Vec_IntSize(vClause),
(ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
if ( RetValue == l_False )
return 1;
assert( RetValue == l_True );
return 0;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Returns 1 if two state are equal.]
Description [Array vState contains indexes of CNF variables for each
flop in the first N time frames (0 < i < k, i < N, k < N).]
SideEffects []
SeeAlso []
***********************************************************************/
int Saig_ManStatesAreEqual( sat_solver * pSat, Vec_Int_t * vState, int nRegs, int i, int k )
{
int * pStateI = (int *)Vec_IntArray(vState) + nRegs * i;
int * pStateK = (int *)Vec_IntArray(vState) + nRegs * k;
int v;
assert( i && k && i < k );
assert( nRegs * k <= Vec_IntSize(vState) );
// check if the states are available
for ( v = 0; v < nRegs; v++ )
if ( pStateI[v] >= 0 && pStateK[v] == -1 )
return 0;
/*
printf( "\nchecking uniqueness\n" );
printf( "%3d : ", i );
for ( v = 0; v < nRegs; v++ )
printf( "%d", sat_solver_var_value(pSat, pStateI[v]) );
printf( "\n" );
printf( "%3d : ", k );
for ( v = 0; v < nRegs; v++ )
printf( "%d", sat_solver_var_value(pSat, pStateK[v]) );
printf( "\n" );
*/
for ( v = 0; v < nRegs; v++ )
if ( pStateI[v] >= 0 )
{
if ( sat_solver_var_value(pSat, pStateI[v]) != sat_solver_var_value(pSat, pStateK[v]) )
return 0;
}
return 1;
}
/**Function*************************************************************
Synopsis [Solve the enumeration problem.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Bmc_EcoSolve( sat_solver * pSat, int Root, Vec_Int_t * vVars )
{
int nBTLimit = 1000000;
Vec_Int_t * vLits = Vec_IntAlloc( Vec_IntSize(vVars) );
int status, i, Div, iVar, nFinal, * pFinal, nIter = 0, RetValue = 0;
int pLits[2], nVars = sat_solver_nvars( pSat );
sat_solver_setnvars( pSat, nVars + 1 );
pLits[0] = Abc_Var2Lit( Root, 0 ); // F = 1
pLits[1] = Abc_Var2Lit( nVars, 0 ); // iNewLit
while ( 1 )
{
// find onset minterm
status = sat_solver_solve( pSat, pLits, pLits + 2, nBTLimit, 0, 0, 0 );
if ( status == l_Undef )
{ RetValue = -1; break; }
if ( status == l_False )
{ RetValue = 1; break; }
assert( status == l_True );
// collect divisor literals
Vec_IntClear( vLits );
Vec_IntPush( vLits, Abc_LitNot(pLits[0]) ); // F = 0
Vec_IntForEachEntry( vVars, Div, i )
Vec_IntPush( vLits, sat_solver_var_literal(pSat, Div) );
// check against offset
status = sat_solver_solve( pSat, Vec_IntArray(vLits), Vec_IntArray(vLits) + Vec_IntSize(vLits), nBTLimit, 0, 0, 0 );
if ( status == l_Undef )
{ RetValue = -1; break; }
if ( status == l_True )
break;
assert( status == l_False );
// compute cube and add clause
nFinal = sat_solver_final( pSat, &pFinal );
Vec_IntClear( vLits );
Vec_IntPush( vLits, Abc_LitNot(pLits[1]) ); // NOT(iNewLit)
printf( "Cube %d : ", nIter );
for ( i = 0; i < nFinal; i++ )
{
if ( pFinal[i] == pLits[0] )
continue;
Vec_IntPush( vLits, pFinal[i] );
iVar = Vec_IntFind( vVars, Abc_Lit2Var(pFinal[i]) ); assert( iVar >= 0 );
printf( "%s%d ", Abc_LitIsCompl(pFinal[i]) ? "+":"-", iVar );
}
printf( "\n" );
status = sat_solver_addclause( pSat, Vec_IntArray(vLits), Vec_IntArray(vLits) + Vec_IntSize(vLits) );
assert( status );
nIter++;
}
// assert( status == l_True );
Vec_IntFree( vLits );
return RetValue;
}
/**Function*************************************************************
Synopsis [Add uniqueness constraint.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Saig_ManAddUniqueness( sat_solver * pSat, Vec_Int_t * vState, int nRegs, int i, int k, int * pnSatVarNum, int * pnClauses )
{
int * pStateI = (int *)Vec_IntArray(vState) + nRegs * i;
int * pStateK = (int *)Vec_IntArray(vState) + nRegs * k;
int v, iVars, nSatVarsOld, RetValue, * pClause;
assert( i && k && i < k );
assert( nRegs * k <= Vec_IntSize(vState) );
// check if the states are available
for ( v = 0; v < nRegs; v++ )
if ( pStateI[v] >= 0 && pStateK[v] == -1 )
{
// printf( "Cannot constrain an incomplete state.\n" );
return;
}
// add XORs
nSatVarsOld = *pnSatVarNum;
for ( v = 0; v < nRegs; v++ )
if ( pStateI[v] >= 0 )
{
*pnClauses += 4;
RetValue = Cnf_DataAddXorClause( pSat, pStateI[v], pStateK[v], (*pnSatVarNum)++ );
if ( RetValue == 0 )
{
printf( "SAT solver became UNSAT.\n" );
return;
}
}
// add OR clause
(*pnClauses)++;
iVars = 0;
pClause = ABC_ALLOC( int, nRegs );
for ( v = nSatVarsOld; v < *pnSatVarNum; v++ )
pClause[iVars++] = toLitCond( v, 0 );
assert( iVars <= nRegs );
RetValue = sat_solver_addclause( pSat, pClause, pClause + iVars );
ABC_FREE( pClause );
if ( RetValue == 0 )
{
printf( "SAT solver became UNSAT.\n" );
return;
}
}
Gia_Man_t * Ssc_PerformSweepingConstr( Gia_Man_t * p, Ssc_Pars_t * pPars )
{
Gia_Man_t * pAig, * pCare, * pResult;
int i;
if ( pPars->fVerbose )
Abc_Print( 0, "SAT sweeping AIG with %d constraints.\n", p->nConstrs );
if ( p->nConstrs == 0 )
{
pAig = Gia_ManDup( p );
pCare = Gia_ManStart( Gia_ManCiNum(p) + 2 );
pCare->pName = Abc_UtilStrsav( "care" );
for ( i = 0; i < Gia_ManCiNum(p); i++ )
Gia_ManAppendCi( pCare );
Gia_ManAppendCo( pCare, 0 );
}
else
{
Vec_Int_t * vOuts = Vec_IntStartNatural( Gia_ManPoNum(p) );
pAig = Gia_ManDupCones( p, Vec_IntArray(vOuts), Gia_ManPoNum(p) - p->nConstrs, 0 );
pCare = Gia_ManDupCones( p, Vec_IntArray(vOuts) + Gia_ManPoNum(p) - p->nConstrs, p->nConstrs, 0 );
Vec_IntFree( vOuts );
}
if ( pPars->fVerbose )
{
printf( "User AIG: " );
Gia_ManPrintStats( pAig, NULL );
printf( "Care AIG: " );
Gia_ManPrintStats( pCare, NULL );
}
pAig = Gia_ManDupLevelized( pResult = pAig );
Gia_ManStop( pResult );
pResult = Ssc_PerformSweeping( pAig, pCare, pPars );
if ( pPars->fAppend )
{
Gia_ManDupAppendShare( pResult, pCare );
pResult->nConstrs = Gia_ManPoNum(pCare);
}
Gia_ManStop( pAig );
Gia_ManStop( pCare );
return pResult;
}
void Wlc_ObjAddFanins( Wlc_Ntk_t * p, Wlc_Obj_t * pObj, Vec_Int_t * vFanins )
{
assert( pObj->nFanins == 0 );
pObj->nFanins = Vec_IntSize(vFanins);
if ( Wlc_ObjHasArray(pObj) )
pObj->pFanins[0] = (int *)Mem_FlexEntryFetch( p->pMemFanin, Vec_IntSize(vFanins) * sizeof(int) );
memcpy( Wlc_ObjFanins(pObj), Vec_IntArray(vFanins), sizeof(int) * Vec_IntSize(vFanins) );
// special treatment of CONST, SELECT and TABLE
if ( pObj->Type == WLC_OBJ_CONST )
pObj->nFanins = 0;
else if ( pObj->Type == WLC_OBJ_BIT_SELECT || pObj->Type == WLC_OBJ_TABLE )
pObj->nFanins = 1;
}
/**Function*************************************************************
Synopsis [Computes partitioning of registers.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManRegCreatePart( Gia_Man_t * p, Vec_Int_t * vPart, int * pnCountPis, int * pnCountRegs, int ** ppMapBack )
{
Gia_Man_t * pNew;
Gia_Obj_t * pObj;
Vec_Int_t * vNodes, * vRoots;
int i, iOut, nCountPis, nCountRegs;
int * pMapBack;
// collect/mark nodes/PIs in the DFS order from the roots
Gia_ManIncrementTravId( p );
vRoots = Vec_IntAlloc( Vec_IntSize(vPart) );
Vec_IntForEachEntry( vPart, iOut, i )
Vec_IntPush( vRoots, Gia_ObjId(p, Gia_ManCo(p, Gia_ManPoNum(p)+iOut)) );
vNodes = Gia_ManCollectNodesCis( p, Vec_IntArray(vRoots), Vec_IntSize(vRoots) );
Vec_IntFree( vRoots );
// unmark register outputs
Vec_IntForEachEntry( vPart, iOut, i )
Gia_ObjSetTravIdPrevious( p, Gia_ManCi(p, Gia_ManPiNum(p)+iOut) );
// count pure PIs
nCountPis = nCountRegs = 0;
Gia_ManForEachPi( p, pObj, i )
nCountPis += Gia_ObjIsTravIdCurrent(p, pObj);
// count outputs of other registers
Gia_ManForEachRo( p, pObj, i )
nCountRegs += Gia_ObjIsTravIdCurrent(p, pObj); // should be !Gia_... ???
if ( pnCountPis )
*pnCountPis = nCountPis;
if ( pnCountRegs )
*pnCountRegs = nCountRegs;
// clean old manager
Gia_ManFillValue(p);
Gia_ManConst0(p)->Value = 0;
// create the new manager
pNew = Gia_ManStart( Vec_IntSize(vNodes) );
// create the PIs
Gia_ManForEachCi( p, pObj, i )
if ( Gia_ObjIsTravIdCurrent(p, pObj) )
pObj->Value = Gia_ManAppendCi(pNew);
// add variables for the register outputs
// create fake POs to hold the register outputs
Vec_IntForEachEntry( vPart, iOut, i )
{
pObj = Gia_ManCi(p, Gia_ManPiNum(p)+iOut);
pObj->Value = Gia_ManAppendCi(pNew);
Gia_ManAppendCo( pNew, pObj->Value );
Gia_ObjSetTravIdCurrent( p, pObj ); // added
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManInterRepar( Aig_Man_t * pMan, int fVerbose )
{
Aig_Man_t * pAigTemp, * pInter, * pBase = NULL;
sat_solver2 * pSat;
Vec_Int_t * vVars;
Cnf_Dat_t * pCnf, * pCnfInter;
Aig_Obj_t * pObj;
int nOuts = Aig_ManCoNum(pMan);
int ShiftP[2], ShiftCnf[2], ShiftOr[2], ShiftAssume;
int Cid, Lit, status, i, k, c;
clock_t clk = clock();
assert( Aig_ManRegNum(pMan) == 0 );
// derive CNFs
pCnf = Cnf_Derive( pMan, nOuts );
// start the solver
pSat = sat_solver2_new();
sat_solver2_setnvars( pSat, 4*pCnf->nVars + 6*nOuts );
// vars: pGlobal + (p0 + A1 + A2 + or0) + (p1 + B1 + B2 + or1) + pAssume;
ShiftP[0] = nOuts;
ShiftP[1] = 2*pCnf->nVars + 3*nOuts;
ShiftCnf[0] = ShiftP[0] + nOuts;
ShiftCnf[1] = ShiftP[1] + nOuts;
ShiftOr[0] = ShiftCnf[0] + 2*pCnf->nVars;
ShiftOr[1] = ShiftCnf[1] + 2*pCnf->nVars;
ShiftAssume = ShiftOr[1] + nOuts;
assert( ShiftAssume + nOuts == pSat->size );
// mark variables of A
for ( i = ShiftCnf[0]; i < ShiftP[1]; i++ )
var_set_partA( pSat, i, 1 );
// add clauses of A, then B
vVars = Vec_IntAlloc( 2*nOuts );
for ( k = 0; k < 2; k++ )
{
// copy A1
Cnf_DataLift( pCnf, ShiftCnf[k] );
for ( i = 0; i < pCnf->nClauses; i++ )
{
Cid = sat_solver2_addclause( pSat, pCnf->pClauses[i], pCnf->pClauses[i+1], 0 );
clause2_set_partA( pSat, Cid, k==0 );
}
// add equality p[k] == A1/B1
Aig_ManForEachCo( pMan, pObj, i )
Aig_ManInterAddBuffer( pSat, ShiftP[k] + i, pCnf->pVarNums[pObj->Id], k==1, k==0 );
// copy A2
Cnf_DataLift( pCnf, pCnf->nVars );
for ( i = 0; i < pCnf->nClauses; i++ )
{
Cid = sat_solver2_addclause( pSat, pCnf->pClauses[i], pCnf->pClauses[i+1], 0 );
clause2_set_partA( pSat, Cid, k==0 );
}
// add comparator (!p[k] ^ A2/B2) == or[k]
Vec_IntClear( vVars );
Aig_ManForEachCo( pMan, pObj, i )
{
Aig_ManInterAddXor( pSat, ShiftP[k] + i, pCnf->pVarNums[pObj->Id], ShiftOr[k] + i, k==1, k==0 );
Vec_IntPush( vVars, toLitCond(ShiftOr[k] + i, 1) );
}
Cid = sat_solver2_addclause( pSat, Vec_IntArray(vVars), Vec_IntArray(vVars) + Vec_IntSize(vVars), 0 );
clause2_set_partA( pSat, Cid, k==0 );
// return to normal
Cnf_DataLift( pCnf, -ShiftCnf[k]-pCnf->nVars );
}
static inline void Kf_ObjSetCuts( Kf_Man_t * p, int i, Vec_Int_t * vVec ) { Vec_IntWriteEntry(&p->vCuts, i, Vec_SetAppend(&p->pMem, Vec_IntArray(vVec), Vec_IntSize(vVec))); }
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Reorder fanins of the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkOrderFaninsById( Abc_Ntk_t * pNtk )
{
Vec_Int_t * vOrder;
Vec_Str_t * vStore;
Abc_Obj_t * pNode;
char * pSop, * pSopNew;
char * pCube, * pCubeNew;
int nVars, i, v, * pOrder;
assert( Abc_NtkHasSop(pNtk) );
vOrder = Vec_IntAlloc( 100 );
vStore = Vec_StrAlloc( 100 );
Abc_NtkForEachNode( pNtk, pNode, i )
{
pSop = (char *)pNode->pData;
nVars = Abc_SopGetVarNum(pSop);
assert( nVars == Abc_ObjFaninNum(pNode) );
Vec_IntClear( vOrder );
for ( v = 0; v < nVars; v++ )
Vec_IntPush( vOrder, v );
pOrder = Vec_IntArray(vOrder);
Vec_IntSelectSortCost( pOrder, nVars, &pNode->vFanins );
// copy the cover
Vec_StrGrow( vStore, Abc_SopGetCubeNum(pSop) * (nVars + 3) + 1 );
memcpy( Vec_StrArray(vStore), pSop, Abc_SopGetCubeNum(pSop) * (nVars + 3) + 1 );
pSopNew = pCubeNew = pSop;
pSop = Vec_StrArray(vStore);
// generate permuted one
Abc_SopForEachCube( pSop, nVars, pCube )
{
for ( v = 0; v < nVars; v++ )
pCubeNew[v] = '-';
for ( v = 0; v < nVars; v++ )
if ( pCube[pOrder[v]] == '0' )
pCubeNew[v] = '0';
else if ( pCube[pOrder[v]] == '1' )
pCubeNew[v] = '1';
pCubeNew += nVars + 3;
}
pNode->pData = pSopNew;
Vec_IntSort( &pNode->vFanins, 0 );
// Vec_IntPrint( vOrder );
}
// suppose AND-gate is A & B = C
// add !A => !C or A + !C
// add !B => !C or B + !C
LitNode = Ssc_ObjSatLit( p, Gia_Obj2Lit(p->pFraig,pNode) );
Vec_IntForEachEntry( vSuper, Lit, i )
{
pLits[0] = Ssc_ObjSatLit( p, Lit );
pLits[1] = Abc_LitNot( LitNode );
RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 2 );
assert( RetValue );
// update literals
Vec_IntWriteEntry( vSuper, i, Abc_LitNot(pLits[0]) );
}
// add A & B => C or !A + !B + C
Vec_IntPush( vSuper, LitNode );
RetValue = sat_solver_addclause( p->pSat, Vec_IntArray(vSuper), Vec_IntArray(vSuper) + Vec_IntSize(vSuper) );
assert( RetValue );
(void) RetValue;
}
/**Function*************************************************************
Synopsis [Collects the supergate.]
Description []
SideEffects []
SeeAlso []
int Pdr_ObjSatVar2( Pdr_Man_t * p, int k, Aig_Obj_t * pObj, int Level, int Pol )
{
Vec_Int_t * vLits;
sat_solver * pSat;
Vec_Int_t * vVar2Ids = (Vec_Int_t *)Vec_PtrEntry(&p->vVar2Ids, k);
int nVarCount = Vec_IntSize(vVar2Ids);
int iVarThis = Pdr_ObjSatVar2FindOrAdd( p, k, pObj );
int * pLit, i, iVar, iClaBeg, iClaEnd, RetValue;
int PolPres = (iVarThis & 3);
iVarThis >>= 2;
if ( Aig_ObjIsCi(pObj) )
return iVarThis;
// Pol = 3;
// if ( nVarCount != Vec_IntSize(vVar2Ids) || (Pol & ~PolPres) )
if ( (Pol & ~PolPres) )
{
*Vec_IntEntryP( p->pvId2Vars + Aig_ObjId(pObj), k ) |= Pol;
iClaBeg = p->pCnf2->pObj2Clause[Aig_ObjId(pObj)];
iClaEnd = iClaBeg + p->pCnf2->pObj2Count[Aig_ObjId(pObj)];
assert( iClaBeg < iClaEnd );
/*
if ( (Pol & ~PolPres) != 3 )
for ( i = iFirstClause; i < iFirstClause + nClauses; i++ )
{
printf( "Clause %5d : ", i );
for ( iVar = 0; iVar < 4; iVar++ )
printf( "%d ", ((unsigned)p->pCnf2->pClaPols[i] >> (2*iVar)) & 3 );
printf( " " );
for ( pLit = p->pCnf2->pClauses[i]; pLit < p->pCnf2->pClauses[i+1]; pLit++ )
printf( "%6d ", *pLit );
printf( "\n" );
}
*/
pSat = Pdr_ManSolver(p, k);
vLits = Vec_WecEntry( p->vVLits, Level );
if ( (Pol & ~PolPres) == 3 )
{
assert( nVarCount + 1 == Vec_IntSize(vVar2Ids) );
for ( i = iClaBeg; i < iClaEnd; i++ )
{
Vec_IntClear( vLits );
Vec_IntPush( vLits, toLitCond( iVarThis, lit_sign(p->pCnf2->pClauses[i][0]) ) );
for ( pLit = p->pCnf2->pClauses[i]+1; pLit < p->pCnf2->pClauses[i+1]; pLit++ )
{
iVar = Pdr_ObjSatVar2( p, k, Aig_ManObj(p->pAig, lit_var(*pLit)), Level+1, 3 );
Vec_IntPush( vLits, toLitCond( iVar, lit_sign(*pLit) ) );
}
RetValue = sat_solver_addclause( pSat, Vec_IntArray(vLits), Vec_IntArray(vLits)+Vec_IntSize(vLits) );
assert( RetValue );
(void) RetValue;
}
}
else // if ( (Pol & ~PolPres) == 2 || (Pol & ~PolPres) == 1 ) // write pos/neg polarity
{
assert( (Pol & ~PolPres) );
for ( i = iClaBeg; i < iClaEnd; i++ )
if ( 2 - !Abc_LitIsCompl(p->pCnf2->pClauses[i][0]) == (Pol & ~PolPres) ) // taking opposite literal
{
Vec_IntClear( vLits );
Vec_IntPush( vLits, toLitCond( iVarThis, Abc_LitIsCompl(p->pCnf2->pClauses[i][0]) ) );
for ( pLit = p->pCnf2->pClauses[i]+1; pLit < p->pCnf2->pClauses[i+1]; pLit++ )
{
iVar = Pdr_ObjSatVar2( p, k, Aig_ManObj(p->pAig, lit_var(*pLit)), Level+1, ((unsigned)p->pCnf2->pClaPols[i] >> (2*(pLit-p->pCnf2->pClauses[i]-1))) & 3 );
Vec_IntPush( vLits, toLitCond( iVar, lit_sign(*pLit) ) );
}
RetValue = sat_solver_addclause( pSat, Vec_IntArray(vLits), Vec_IntArray(vLits)+Vec_IntSize(vLits) );
assert( RetValue );
(void) RetValue;
}
}
static inline int Swp_ManLit2Lit( Swp_Man_t * p, int Lit ) { assert( Vec_IntEntry(p->vId2Lit, Abc_Lit2Var(Lit)) ); return Abc_Lit2LitL( Vec_IntArray(p->vId2Lit), Lit ); }
