INT32 wmt_plat_wake_lock_ctrl(ENUM_WL_OP opId)
{
#ifdef CFG_WMT_WAKELOCK_SUPPORT
static INT32 counter;
INT32 status;
INT32 ret = 0;
ret = mutex_lock_killable(&gOsSLock);
if (ret) {
WMT_PLAT_ERR_FUNC("--->lock gOsSLock failed, ret=%d\n", ret);
return ret;
}
if (WL_OP_GET == opId)
++counter;
else if (WL_OP_PUT == opId)
--counter;
mutex_unlock(&gOsSLock);
if (WL_OP_GET == opId && counter == 1) {
#ifdef CONFIG_PM_WAKELOCKS
__pm_stay_awake(&wmtWakeLock);
status = wmtWakeLock.active;
#else
wake_lock(&wmtWakeLock);
status = wake_lock_active(&wmtWakeLock);
#endif
WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_lock(%d), counter(%d)\n", status, counter);
} else if (WL_OP_PUT == opId && counter == 0) {
#ifdef CONFIG_PM_WAKELOCKS
__pm_relax(&wmtWakeLock);
status = wmtWakeLock.active;
#else
wake_unlock(&wmtWakeLock);
status = wake_lock_active(&wmtWakeLock);
#endif
WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_unlock(%d), counter(%d)\n", status, counter);
} else {
#ifdef CONFIG_PM_WAKELOCKS
status = wmtWakeLock.active;
#else
status = wake_lock_active(&wmtWakeLock);
#endif
WMT_PLAT_WARN_FUNC("WMT-PLAT: wakelock status(%d), counter(%d)\n", status, counter);
}
return 0;
#else
WMT_PLAT_WARN_FUNC("WMT-PLAT: host awake function is not supported.\n");
return 0;
#endif
}
INT32
wmt_plat_init (UINT32 co_clock_en)
{
CMB_STUB_CB stub_cb;
INT32 iret;
/*init wmt function ctrl wakelock if wake lock is supported by host platform*/
if(co_clock_en)
{
wmt_plat_soc_co_clock_flag_set(1);
}else
{
wmt_plat_soc_co_clock_flag_set(0);
}
stub_cb.aif_ctrl_cb = wmt_plat_audio_ctrl;
stub_cb.func_ctrl_cb = wmt_plat_func_ctrl;
stub_cb.thermal_query_cb = wmt_plat_thermal_ctrl;
stub_cb.deep_idle_ctrl_cb = wmt_plat_deep_idle_ctrl;
stub_cb.size = sizeof(stub_cb);
/* register to cmb_stub */
iret = mtk_wcn_cmb_stub_reg(&stub_cb);
#ifdef CFG_WMT_WAKELOCK_SUPPORT
wake_lock_init(&wmtWakeLock, WAKE_LOCK_SUSPEND, "wmtFuncCtrl");
mutex_init(&gOsSLock);
#endif
iret += mtk_wcn_consys_hw_init();
spin_lock_init(&gbgfIrqBle.lock);
WMT_PLAT_DBG_FUNC("WMT-PLAT: ALPS platform init (%d)\n", iret);
return 0;
}
INT32 wmt_plat_i2s_ctrl(ENUM_PIN_STATE state)
{
/* TODO: [NewFeature][GeorgeKuo]: GPIO_I2Sx is changed according to different project. */
/* TODO: provide a translation table in board_custom.h for different ALPS project customization. */
#if defined(CONFIG_MTK_GPIO_LEGACY)
#if defined(FM_DIGITAL_INPUT) || defined(FM_DIGITAL_OUTPUT)
#if defined(GPIO_COMBO_I2S_CK_PIN)
switch (state) {
case PIN_STA_INIT:
case PIN_STA_MUX:
mt_set_gpio_mode(GPIO_COMBO_I2S_CK_PIN, GPIO_COMBO_I2S_CK_PIN_M_I2S0_CK);
mt_set_gpio_mode(GPIO_COMBO_I2S_WS_PIN, GPIO_COMBO_I2S_WS_PIN_M_I2S0_WS);
mt_set_gpio_mode(GPIO_COMBO_I2S_DAT_PIN, GPIO_COMBO_I2S_DAT_PIN_M_I2S0_DAT);
WMT_PLAT_DBG_FUNC("WMT-PLAT:I2S init (I2S0 system)\n");
break;
case PIN_STA_IN_L:
case PIN_STA_DEINIT:
mt_set_gpio_mode(GPIO_COMBO_I2S_CK_PIN, GPIO_COMBO_I2S_CK_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_I2S_CK_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_COMBO_I2S_CK_PIN, GPIO_OUT_ZERO);
mt_set_gpio_mode(GPIO_COMBO_I2S_WS_PIN, GPIO_COMBO_I2S_WS_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_I2S_WS_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_COMBO_I2S_WS_PIN, GPIO_OUT_ZERO);
mt_set_gpio_mode(GPIO_COMBO_I2S_DAT_PIN, GPIO_COMBO_I2S_DAT_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_I2S_DAT_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_COMBO_I2S_DAT_PIN, GPIO_OUT_ZERO);
WMT_PLAT_DBG_FUNC("WMT-PLAT:I2S deinit (out 0)\n");
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:Warnning, invalid state(%d) on I2S Group\n", state);
break;
}
#else
WMT_PLAT_ERR_FUNC("[MT6620]Error:FM digital mode set, but no I2S GPIOs defined\n");
#endif
#else
WMT_PLAT_INFO_FUNC
("[MT6620]warnning:FM digital mode is not set, no I2S GPIO settings should be modified by combo driver\n");
#endif
#else /* #if defined(CONFIG_MTK_GPIO_LEGACY) */
#endif
return 0;
}
static INT32 mtk_wmt_probe(struct platform_device *pdev)
{
#if !defined(CONFIG_MTK_CLKMGR)
clk_scp_conn_main = devm_clk_get(&pdev->dev, "conn");
if (IS_ERR(clk_scp_conn_main)) {
WMT_PLAT_ERR_FUNC("[CCF]cannot get clk_scp_conn_main clock.\n");
return PTR_ERR(clk_scp_conn_main);
}
WMT_PLAT_DBG_FUNC("[CCF]clk_scp_conn_main=%p\n", clk_scp_conn_main);
clk_infra_conn_main = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(clk_infra_conn_main)) {
WMT_PLAT_ERR_FUNC("[CCF]cannot get clk_infra_conn_main clock.\n");
return PTR_ERR(clk_infra_conn_main);
}
WMT_PLAT_DBG_FUNC("[CCF]clk_infra_conn_main=%p\n", clk_infra_conn_main);
#endif /* !defined(CONFIG_MTK_CLKMGR) */
#if CONSYS_PMIC_CTRL_ENABLE
#if !defined(CONFIG_MTK_PMIC_LEGACY)
reg_VCN18 = regulator_get(&pdev->dev, "vcn18");
if (!reg_VCN18)
WMT_PLAT_ERR_FUNC("Regulator_get VCN_1V8 fail\n");
reg_VCN28 = regulator_get(&pdev->dev, "vcn28");
if (!reg_VCN28)
WMT_PLAT_ERR_FUNC("Regulator_get VCN_2V8 fail\n");
reg_VCN33_BT = regulator_get(&pdev->dev, "vcn33_bt");
if (!reg_VCN33_BT)
WMT_PLAT_ERR_FUNC("Regulator_get VCN33_BT fail\n");
reg_VCN33_WIFI = regulator_get(&pdev->dev, "vcn33_wifi");
if (!reg_VCN33_WIFI)
WMT_PLAT_ERR_FUNC("Regulator_get VCN33_WIFI fail\n");
#endif
#endif
#if !defined(CONFIG_MTK_GPIO_LEGACY)
consys_pinctrl = devm_pinctrl_get(&pdev->dev);
if (IS_ERR(consys_pinctrl)) {
WMT_PLAT_ERR_FUNC("cannot find consys pinctrl.\n");
return PTR_ERR(consys_pinctrl);
}
#endif /* !defined(CONFIG_MTK_GPIO_LEGACY) */
return 0;
}
INT32
wmt_plat_bgf_eint_ctrl (
ENUM_PIN_STATE state
)
{
#ifdef GPIO_COMBO_BGF_EINT_PIN
switch(state)
{
case PIN_STA_INIT:
/*set to gpio input low, pull down enable*/
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_BGF_EINT_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_select(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_DOWN);
mt_set_gpio_pull_enable(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_ENABLE);
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt init(in pd) \n");
break;
case PIN_STA_MUX:
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_GPIO);
mt_set_gpio_pull_enable(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_UP);
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_EINT);
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt mux (eint) \n");
break;
case PIN_STA_IN_L:
case PIN_STA_DEINIT:
/*set to gpio input low, pull down enable*/
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_BGF_EINT_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_select(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_DOWN);
mt_set_gpio_pull_enable(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_ENABLE);
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt deinit(in pd) \n");
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:Warnning, invalid state(%d) on BGF EINT\n", state);
break;
}
#else
WMT_PLAT_INFO_FUNC("WMT-PLAT:BGF EINT not defined\n");
#endif
return 0;
}
INT32 wmt_plat_wake_lock_ctrl(ENUM_WL_OP opId)
{
#ifdef CFG_WMT_WAKELOCK_SUPPORT
static INT32 counter = 0;
INT32 ret = 0;
ret = mutex_lock_killable( &gOsSLock);
if (ret) {
WMT_PLAT_ERR_FUNC("--->lock gOsSLock failed, ret=%d\n", ret);
return ret;
}
if (WL_OP_GET == opId)
{
++counter;
}else if (WL_OP_PUT == opId)
{
--counter;
}
mutex_unlock( &gOsSLock);
if (WL_OP_GET == opId && counter == 1)
{
wake_lock(&wmtWakeLock);
WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_lock(%d), counter(%d)\n", wake_lock_active(&wmtWakeLock), counter);
}
else if (WL_OP_PUT == opId && counter == 0)
{
wake_unlock(&wmtWakeLock);
WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_unlock(%d), counter(%d)\n", wake_lock_active(&wmtWakeLock), counter);
}
else
{
WMT_PLAT_WARN_FUNC("WMT-PLAT: wakelock status(%d), counter(%d)\n", wake_lock_active(&wmtWakeLock), counter);
}
return 0;
#else
WMT_PLAT_WARN_FUNC("WMT-PLAT: host awake function is not supported.");
return 0;
#endif
}
INT32 mtk_wcn_consys_hw_bt_paldo_ctrl(UINT32 enable)
{
/* spin_lock_irqsave(&gBtWifiV33.lock,gBtWifiV33.flags); */
if (enable) {
if (1 == gBtWifiV33.counter) {
gBtWifiV33.counter++;
WMT_PLAT_DBG_FUNC("V33 has been enabled,counter(%d)\n", gBtWifiV33.counter);
} else if (2 == gBtWifiV33.counter) {
WMT_PLAT_DBG_FUNC("V33 has been enabled,counter(%d)\n", gBtWifiV33.counter);
} else {
#if CONSYS_PMIC_CTRL_ENABLE
/*do BT PMIC on,depenency PMIC API ready */
/*switch BT PALDO control from SW mode to HW mode:0x416[5]-->0x1 */
/* VOL_DEFAULT, VOL_3300, VOL_3400, VOL_3500, VOL_3600 */
hwPowerOn(MT6325_POWER_LDO_VCN33, VOL_3300, "wcn_drv");
mt6325_upmu_set_rg_vcn33_on_ctrl(1);
#endif
WMT_PLAT_INFO_FUNC("WMT do BT/WIFI v3.3 on\n");
gBtWifiV33.counter++;
}
} else {
if (1 == gBtWifiV33.counter) {
/*do BT PMIC off */
/*switch BT PALDO control from HW mode to SW mode:0x416[5]-->0x0 */
#if CONSYS_PMIC_CTRL_ENABLE
mt6325_upmu_set_rg_vcn33_on_ctrl(0);
hwPowerDown(MT6325_POWER_LDO_VCN33, "wcn_drv");
#endif
WMT_PLAT_INFO_FUNC("WMT do BT/WIFI v3.3 off\n");
gBtWifiV33.counter--;
} else if (2 == gBtWifiV33.counter) {
gBtWifiV33.counter--;
WMT_PLAT_DBG_FUNC("V33 no need disabled,counter(%d)\n", gBtWifiV33.counter);
} else {
WMT_PLAT_DBG_FUNC("V33 has been disabled,counter(%d)\n", gBtWifiV33.counter);
}
}
/* spin_unlock_irqrestore(&gBtWifiV33.lock,gBtWifiV33.flags); */
return 0;
}
INT32
wmt_plat_deinit (VOID)
{
INT32 iret = 0;
/* 2. unreg to cmb_stub */
iret = mtk_wcn_cmb_stub_unreg();
/*3. wmt wakelock deinit*/
#ifdef CFG_WMT_WAKELOCK_SUPPORT
wake_lock_destroy(&wmtWakeLock);
mutex_destroy(&gOsSLock);
WMT_PLAT_DBG_FUNC("destroy wmtWakeLock\n");
#endif
iret += mtk_wcn_consys_hw_deinit();
WMT_PLAT_DBG_FUNC("WMT-PLAT: ALPS platform init (%d)\n", iret);
return 0;
}
INT32 mtk_wcn_consys_hw_gpio_ctrl(UINT32 on)
{
INT32 iRet = 0;
WMT_PLAT_DBG_FUNC("CONSYS-HW-GPIO-CTRL(0x%08x), start\n", on);
if (on) {
/*if external modem used,GPS_SYNC still needed to control */
iRet += wmt_plat_gpio_ctrl(PIN_GPS_SYNC, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_GPS_LNA, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_INIT);
/* TODO: [FixMe][GeorgeKuo] double check if BGF_INT is implemented ok */
/* iRet += wmt_plat_gpio_ctrl(PIN_BGF_EINT, PIN_STA_MUX); */
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_INIT);
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_EINT_DIS);
WMT_PLAT_DBG_FUNC("CONSYS-HW, BGF IRQ registered and disabled\n");
} else {
/* set bgf eint/all eint to deinit state, namely input low state */
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_EINT_DIS);
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_DEINIT);
WMT_PLAT_DBG_FUNC("CONSYS-HW, BGF IRQ unregistered and disabled\n");
/* iRet += wmt_plat_gpio_ctrl(PIN_BGF_EINT, PIN_STA_DEINIT); */
/*if external modem used,GPS_SYNC still needed to control */
iRet += wmt_plat_gpio_ctrl(PIN_GPS_SYNC, PIN_STA_DEINIT);
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_DEINIT);
/* deinit gps_lna */
iRet += wmt_plat_gpio_ctrl(PIN_GPS_LNA, PIN_STA_DEINIT);
}
WMT_PLAT_DBG_FUNC("CONSYS-HW-GPIO-CTRL(0x%08x), finish\n", on);
return iRet;
}
UINT8 *mtk_wcn_consys_emi_virt_addr_get(UINT32 ctrl_state_offset)
{
UINT8 *p_virtual_addr = NULL;
if(!pEmibaseaddr)
{
WMT_PLAT_ERR_FUNC("EMI base address is NULL\n");
return NULL;
}
WMT_PLAT_DBG_FUNC("ctrl_state_offset(%08x)\n",ctrl_state_offset);
p_virtual_addr = pEmibaseaddr + ctrl_state_offset;
return p_virtual_addr;
}
INT32 wmt_plat_init(UINT32 co_clock_type)
{
CMB_STUB_CB stub_cb;
INT32 iret;
/*init wmt function ctrl wakelock if wake lock is supported by host platform */
wmt_plat_soc_co_clock_flag_set(co_clock_type);
stub_cb.aif_ctrl_cb = wmt_plat_audio_ctrl;
stub_cb.func_ctrl_cb = wmt_plat_func_ctrl;
stub_cb.thermal_query_cb = wmt_plat_thermal_ctrl;
stub_cb.deep_idle_ctrl_cb = wmt_plat_deep_idle_ctrl;
stub_cb.wmt_do_reset_cb = NULL;
stub_cb.size = sizeof(stub_cb);
/* register to cmb_stub */
iret = mtk_wcn_cmb_stub_reg(&stub_cb);
#ifdef CFG_WMT_WAKELOCK_SUPPORT
#ifdef CONFIG_PM_WAKELOCKS
wakeup_source_init(&wmtWakeLock, "wmtFuncCtrl");
#else
wake_lock_init(&wmtWakeLock, WAKE_LOCK_SUSPEND, "wmtFuncCtrl");
#endif
mutex_init(&gOsSLock);
#endif
#if CONSYS_BT_WIFI_SHARE_V33
gBtWifiV33.counter = 0;
spin_lock_init(&gBtWifiV33.lock);
#endif
iret += mtk_wcn_consys_hw_init();
spin_lock_init(&gbgfIrqBle.lock);
WMT_PLAT_DBG_FUNC("WMT-PLAT: ALPS platform init (%d)\n", iret);
return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on, UINT32 co_clock_type)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n", on);
if (on) {
WMT_PLAT_DBG_FUNC("++\n");
/*step1.PMIC ctrl*/
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol */
/*1.AP power on VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800... */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN18, VOL_1800, "wcn_drv");
#else
if (reg_VCN18) {
regulator_set_voltage(reg_VCN18, VOL_1800, VOL_1800);
if (regulator_enable(reg_VCN18))
WMT_PLAT_ERR_FUNC("enable VCN18 fail\n");
else
WMT_PLAT_DBG_FUNC("enable VCN18 ok\n");
}
#endif
udelay(150);
if (co_clock_type) {
/*step0,clk buf ctrl */
WMT_PLAT_INFO_FUNC("co clock type(%d),turn on clk buf\n", co_clock_type);
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 1);
#endif
/*if co-clock mode: */
/*2.set VCN28 to SW control mode (with PMIC_WRAP API) */
/*turn on VCN28 LDO only when FMSYS is activated" */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
} else {
/*if NOT co-clock: */
/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 1);
/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)" */
/*fix vcn28 not balance warning */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
#else
if (reg_VCN28) {
regulator_set_voltage(reg_VCN28, VOL_2800, VOL_2800);
if (regulator_enable(reg_VCN28))
WMT_PLAT_ERR_FUNC("enable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("enable VCN_2V8 ok\n");
}
#endif
}
#endif
/*step2.MTCMOS ctrl*/
#ifdef CONFIG_OF /*use DT */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET),
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) |
CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner. */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT &
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) &
~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until chipid is returned 0x18070008 */
while (retry-- > 0) {
consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
WMT_PLAT_ERR_FUNC("Read CONSYS chipId(0x%08x)", consysHwChipId);
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET,
CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) |
CONSYS_MCU_CFG_ACR_MBIST_BIT);
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88 (key)" */
CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) &
~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
#else /*use HADRCODE, maybe no use.. */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT |
CONSYS_CPU_SW_RST_CTRL_KEY));
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN, CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) & ~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until 6752 is returned 0x18070008 32'h6752 */
while (retry-- > 0) {
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)", CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG,
CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*update ANA_WBG(AFE) CR. AFE setting file: AP Offset = 0x180B2000 */
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88(key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) |
CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(20); /* msleep < 20ms can sleep for up to 20ms */
} else {
#ifdef CONFIG_OF
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
WMT_PLAT_DBG_FUNC("[CCF] clk_disable_unprepare(clk_infra_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) |
CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) &
CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#else
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN,
CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) | CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#endif
#if CONSYS_PMIC_CTRL_ENABLE
if (co_clock_type) {
/*VCN28 has been turned off by GPS OR FM */
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 0);
#endif
} else {
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN28, "wcn_drv");
#else
if (reg_VCN28) {
if (regulator_disable(reg_VCN28))
WMT_PLAT_ERR_FUNC("disable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_2V8 ok\n");
}
#endif
}
/*AP power off MT6625L VCN_1V8 LDO */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN18, "wcn_drv");
#else
if (reg_VCN18) {
if (regulator_disable(reg_VCN18))
WMT_PLAT_ERR_FUNC("disable VCN_1V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_1V8 ok\n");
}
#endif
#endif
}
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n", on);
return 0;
}
INT32
wmt_plat_eirq_ctrl (
ENUM_PIN_ID id,
ENUM_PIN_STATE state
)
{
INT32 iret;
// TODO: [ChangeFeature][GeorgeKuo]: use another function to handle this, as done in gpio_ctrls
if ( (PIN_STA_INIT != state )
&& (PIN_STA_DEINIT != state )
&& (PIN_STA_EINT_EN != state )
&& (PIN_STA_EINT_DIS != state ) ) {
WMT_PLAT_WARN_FUNC("WMT-PLAT:invalid PIN_STATE(%d) in eirq_ctrl for PIN(%d)\n", state, id);
return -1;
}
iret = -2;
switch (id) {
case PIN_BGF_EINT:
#if 1
if (PIN_STA_INIT == state) {
iret = request_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,
(irq_handler_t)wmt_plat_bgf_irq_isr,
IRQF_TRIGGER_LOW,
"BTIF_WAKEUP_IRQ",
NULL);
if(iret)
{
WMT_PLAT_ERR_FUNC("request_irq fail,irq_no(%d),iret(%d)\n",MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,iret);
return iret;
}
gbgfIrqBle.counter = 1;
}
else if (PIN_STA_EINT_EN == state) {
spin_lock_irqsave(&gbgfIrqBle.lock,gbgfIrqBle.flags);
if(gbgfIrqBle.counter)
{
WMT_PLAT_DBG_FUNC("BGF INT has been enabled,counter(%d)\n",gbgfIrqBle.counter);;
}
else
{
enable_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID);
gbgfIrqBle.counter++;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (en) \n");
spin_unlock_irqrestore(&gbgfIrqBle.lock,gbgfIrqBle.flags);
}
else if (PIN_STA_EINT_DIS == state) {
spin_lock_irqsave(&gbgfIrqBle.lock,gbgfIrqBle.flags);
if(!gbgfIrqBle.counter)
{
WMT_PLAT_INFO_FUNC("BGF INT has been disabled,counter(%d)\n",gbgfIrqBle.counter);;
}
else
{
disable_irq_nosync(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID);
gbgfIrqBle.counter--;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (dis) \n");
spin_unlock_irqrestore(&gbgfIrqBle.lock,gbgfIrqBle.flags);
}
else {
free_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,NULL);
/* de-init: nothing to do in ALPS, such as un-registration... */
}
#else
WMT_PLAT_INFO_FUNC("WMT-PLAT:BGF EINT not defined\n", state);
#endif
iret = 0;
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:unsupported EIRQ(PIN_ID:%d) in eirq_ctrl\n", id);
iret = -1;
break;
}
return iret;
}
INT32 wmt_plat_eirq_ctrl(ENUM_PIN_ID id, ENUM_PIN_STATE state)
{
#ifdef CONFIG_OF
struct device_node *node;
unsigned int irq_info[3] = { 0, 0, 0 };
#endif
INT32 iret = -EINVAL;
static INT32 bgf_irq_num = -1;
static UINT32 bgf_irq_flag;
/* TODO: [ChangeFeature][GeorgeKuo]: use another function to handle this, as done in gpio_ctrls */
if ((PIN_STA_INIT != state)
&& (PIN_STA_DEINIT != state)
&& (PIN_STA_EINT_EN != state)
&& (PIN_STA_EINT_DIS != state)) {
WMT_PLAT_WARN_FUNC("WMT-PLAT:invalid PIN_STATE(%d) in eirq_ctrl for PIN(%d)\n", state, id);
return -1;
}
switch (id) {
case PIN_BGF_EINT:
if (PIN_STA_INIT == state) {
#ifdef CONFIG_OF
node = of_find_compatible_node(NULL, NULL, "mediatek,mt6735-consys");
if (node) {
bgf_irq_num = irq_of_parse_and_map(node, 0);
/* get the interrupt line behaviour */
if (of_property_read_u32_array(node, "interrupts", irq_info, ARRAY_SIZE(irq_info))) {
WMT_PLAT_ERR_FUNC("get irq flags from DTS fail!!\n");
return iret;
}
bgf_irq_flag = irq_info[2];
WMT_PLAT_INFO_FUNC("get irq id(%d) and irq trigger flag(%d) from DT\n", bgf_irq_num,
bgf_irq_flag);
} else {
WMT_PLAT_ERR_FUNC("[%s] can't find CONSYS compatible node\n", __func__);
return iret;
}
#else
bgf_irq_num = MT_CONN2AP_BTIF_WAKEUP_IRQ_ID;
bgf_irq_flag = IRQF_TRIGGER_LOW;
#endif
iret = request_irq(bgf_irq_num, wmt_plat_bgf_irq_isr, bgf_irq_flag, "BTIF_WAKEUP_IRQ", NULL);
if (iret) {
WMT_PLAT_ERR_FUNC("request_irq fail,irq_no(%d),iret(%d)\n", bgf_irq_num, iret);
return iret;
}
gbgfIrqBle.counter = 1;
} else if (PIN_STA_EINT_EN == state) {
spin_lock_irqsave(&gbgfIrqBle.lock, gbgfIrqBle.flags);
if (gbgfIrqBle.counter) {
WMT_PLAT_DBG_FUNC("BGF INT has been enabled,counter(%d)\n", gbgfIrqBle.counter);
} else {
enable_irq(bgf_irq_num);
gbgfIrqBle.counter++;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (en)\n");
spin_unlock_irqrestore(&gbgfIrqBle.lock, gbgfIrqBle.flags);
} else if (PIN_STA_EINT_DIS == state) {
spin_lock_irqsave(&gbgfIrqBle.lock, gbgfIrqBle.flags);
if (!gbgfIrqBle.counter) {
WMT_PLAT_INFO_FUNC("BGF INT has been disabled,counter(%d)\n", gbgfIrqBle.counter);
} else {
disable_irq_nosync(bgf_irq_num);
gbgfIrqBle.counter--;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (dis)\n");
spin_unlock_irqrestore(&gbgfIrqBle.lock, gbgfIrqBle.flags);
} else {
free_irq(bgf_irq_num, NULL);
/* de-init: nothing to do in ALPS, such as un-registration... */
}
iret = 0;
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:unsupported EIRQ(PIN_ID:%d) in eirq_ctrl\n", id);
iret = -1;
break;
}
return iret;
}
static INT32 wmt_plat_gps_lna_ctrl(ENUM_PIN_STATE state)
{
#if !defined(CONFIG_MTK_GPIO_LEGACY)
static struct pinctrl_state *gps_lna_init;
static struct pinctrl_state *gps_lna_oh;
static struct pinctrl_state *gps_lna_ol;
static struct pinctrl *consys_pinctrl;
WMT_PLAT_DBG_FUNC("ENTER++\n");
consys_pinctrl = mtk_wcn_consys_get_pinctrl();
if (NULL == consys_pinctrl) {
WMT_PLAT_ERR_FUNC("get consys pinctrl fail\n");
return -1;
}
gps_lna_init = pinctrl_lookup_state(consys_pinctrl, "gps_lna_state_init");
if (NULL == gps_lna_init) {
WMT_PLAT_ERR_FUNC("Cannot find gps lna pin init state!\n");
return -2;
}
gps_lna_oh = pinctrl_lookup_state(consys_pinctrl, "gps_lna_state_oh");
if (NULL == gps_lna_oh) {
WMT_PLAT_ERR_FUNC("Cannot find gps lna pin oh state!\n");
return -3;
}
gps_lna_ol = pinctrl_lookup_state(consys_pinctrl, "gps_lna_state_ol");
if (NULL == gps_lna_ol) {
WMT_PLAT_ERR_FUNC("Cannot find gps lna pin ol state!\n");
return -4;
}
switch (state) {
case PIN_STA_INIT:
case PIN_STA_DEINIT:
pinctrl_select_state(consys_pinctrl, gps_lna_init);
WMT_PLAT_INFO_FUNC("set gps lna to init\n");
break;
case PIN_STA_OUT_H:
pinctrl_select_state(consys_pinctrl, gps_lna_oh);
WMT_PLAT_INFO_FUNC("set gps lna to oh\n");
break;
case PIN_STA_OUT_L:
pinctrl_select_state(consys_pinctrl, gps_lna_ol);
WMT_PLAT_INFO_FUNC("set gps lna to ol\n");
break;
default:
WMT_PLAT_WARN_FUNC("%d mode not defined for gps lna pin !!!\n", state);
break;
}
return 0;
#else
#ifdef GPIO_GPS_LNA_PIN
switch (state) {
case PIN_STA_INIT:
case PIN_STA_DEINIT:
mt_set_gpio_pull_enable(GPIO_GPS_LNA_PIN, GPIO_PULL_DISABLE);
mt_set_gpio_dir(GPIO_GPS_LNA_PIN, GPIO_DIR_OUT);
mt_set_gpio_mode(GPIO_GPS_LNA_PIN, GPIO_GPS_LNA_PIN_M_GPIO);
mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
break;
case PIN_STA_OUT_H:
mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ONE);
break;
case PIN_STA_OUT_L:
mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
break;
default:
WMT_PLAT_WARN_FUNC("%d mode not defined for gps lna pin !!!\n", state);
break;
}
return 0;
#else
WMT_PLAT_WARN_FUNC("host gps lna pin not defined!!!\n");
return 0;
#endif
#endif /* !defined(CONFIG_MTK_GPIO_LEGACY) */
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
#if PWR_ON_OFF_API_AVALIABLE
INT32 iRet = -1;
#endif
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
WMT_PLAT_DBG_FUNC("CONSYS_EMI_MAPPING dump before power on/off(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
if(mtk_wcn_regulator_get()){
WMT_PLAT_ERR_FUNC("regulator_get fail\n");
return -1;
}
/*need PMIC driver provide new API protocol */
/*1.AP power on MT6350 VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 0x0510[1] "1'b0 0x0512[14]" 1'b1"*/
pmic_set_register_value(PMIC_VCN_1V8_ON_CTRL,0);
if(reg_V18){
regulator_enable(reg_V18);
WMT_PLAT_INFO_FUNC("wmt_dev enable VCN_1V8\n");
}
udelay(300);
if(co_clock_en)
{
/*if co-clock mode:*/
/*2.set RF XO BUF source from CellularRF DA_XOBUF_SEL 0x1000513C[7:6] 2'b10*/
CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) & ~(0x1 << 6) );
CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) | (0x1 << 7) );
WMT_PLAT_INFO_FUNC("co_clock mode reg dump:XO BUFFER(0x%08x)\n",CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET));
}
else
{
/*if NOT co-clock:*/
/*2.1 switch VCN28 to HW control mode (with PMIC_WRAP API) RG_VCN28_ON_CTRL 0x041C[14] 1'b1*/
pmic_set_register_value(PMIC_VCN28_ON_CTRL,1);
/*2.2 turn on VCN28 LDO (with PMIC_WRAP API) DA_XOBUF_SEL 0x1000513C[7:6]" " 2'b11"*/
CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) | ((0x1 << 7) |(0x1 << 6)));
WMT_PLAT_INFO_FUNC("NOT co_clock mode reg dump:XO BUFFER(0x%08x)\n",CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET));
udelay(300);
}
#endif
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)"*/
CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET), CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) | CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
/*turn on top clock gating enable TOP_CLKCG_CLR 0x10000084[26] 1'b1 */
// CONSYS_REG_WRITE((conn_reg.topckgen_base + CONSYS_TOP_CLKCG_CLR_OFFSET), CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOP_CLKCG_CLR_OFFSET) | CONSYS_TOP_CLKCG_BIT);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);
#if PWR_ON_OFF_API_AVALIABLE
iRet = conn_power_on(); //consult clkmgr owner.
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_on ok\n");
}
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)));
/*4.write conn_top1_mem_PD=0, power on MCU memory (MT6572 with the same addr) sram_conn_pd 0x10006280 [3] 1'b1 */
//CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SRAM_CONN_PD_BIT);
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on_s 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack_s 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)));
/*9.release connsys ISO, conn_top1_iso_en=0 (MT6572 with the same addr) conn_spm_pwr_iso 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 (MT6572 with the same addr) conn_spm_pwr_rst_b 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_RST_BIT);
/*Disable AXI bus protect 0x10001220[8] 0x10001220[9] 1'b0 1'b0*/
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET, CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) & ~CONSYS_PROT_MASK);
// while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK) {
// }
#endif
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
/*11.26M is ready now, delay 10us for mem_pd de-assert*/
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++??*/
/*12.poll CONNSYS CHIP ID until 6580 is returned 0x18070008 32'h6580 */
while (retry-- > 0)
{
consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
if(consysHwChipId == 0x6580) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
break;
} else {
WMT_PLAT_INFO_FUNC("Read CONSYS chipId(0x%08x)",consysHwChipId);
}
msleep(20);
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 "[3:0] ROM DELSEL [7:4] RAM4Kx32 DELSEL" ??*/
/*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST (default write "1") ACR 0x18070110[18] 1'b1*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET, CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*"update ANA_WBG(AFE) CR. AFE setting file: MT6752_AFE_SW_patch_REG_xxxx.xlsx" AP Offset = 0x180B2000" AP Offset = 0x180B2000*/
#if 0
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset (need to check MT6752) 0x10007018 "[12]=1'b0 [31:24]=8'h88 (key)"*/
CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) & ~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
msleep(5);
}else{
#if PWR_ON_OFF_API_AVALIABLE
WMT_PLAT_INFO_FUNC("\n conn_power_off begin\n");
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off();//consult clkmgr owner
WMT_PLAT_INFO_FUNC("\n conn_power_off end\n");
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_off ok\n");
}
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET, CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) | CONSYS_PROT_MASK);
//while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
// count++;
// if(count>1000)
// break;
//}
}
/*release connsys ISO, conn_top1_iso_en=1 (MT6572 with the same addr) 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 (MT6572 with the same addr) 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |CONSYS_CLK_CTRL_BIT);
/*DA_WBG_EN_XBUF=0 */
/*wait 1us */
udelay(1);
/*write conn_top1_mem_PD=1, power off MCU memory (MT6572 with the same addr) 0x10006280 [8] 1'b0 */
//CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SRAM_CONN_PD_BIT);
/*write conn_top1_pwr_on=0, power off conn_top1 (MT6572 with the same addr) 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#if CONSYS_PMIC_CTRL_ENABLE
/*set VCN_28 to SW control mode (with PMIC_WRAP API) "1. VCN28_ON_CTRL "0x041C[14] 1'b0*/
//mt6325_upmu_set_rg_vcn28_on_ctrl(0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" 2. RG_VCN28_EN" 0x041C[12]" 1'b0*/
//hwPowerDown(MT6325_POWER_LDO_VCN28, "wcn_drv");
/*AP power off MT6323 VCN_1V8 LDO (with PMIC_WRAP API) RG_VCN18_ON_CTRL "0x0510[1] "1'b0 RG_VCN18_EN" 0x0512[14]" 1'b0"*/
pmic_set_register_value(PMIC_VCN_1V8_ON_CTRL,0);
if(reg_V18){
regulator_disable(reg_V18);
WMT_PLAT_INFO_FUNC("wmt_dev disable VCN_1V8\n");
}
#endif
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
#if PWR_ON_OFF_API_AVALIABLE
INT32 iRet = -1;
#endif
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
WMT_PLAT_DBG_FUNC("CONSYS_EMI_MAPPING dump before power on/off(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol */
/*1.AP power on MT6325 VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 "0x0512[1] "1'b0 0x0512[14]" 1'b1"*/
mt6325_upmu_set_rg_vcn18_on_ctrl(0);
/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800, VOL_2500, VOL_2800, VOL_3000, VOL_3300*/
hwPowerOn(MT6325_POWER_LDO_VCN18, VOL_1800, "wcn_drv");
udelay(150);
if(co_clock_en)
{
/*if co-clock mode:*/
/*2.set VCN28 to SW control mode (with PMIC_WRAP API) VCN28_ON_CTRL 0x041C[14] 1'b0*/
/*turn on VCN28 LDO only when FMSYS is activated" */
mt6325_upmu_set_rg_vcn28_on_ctrl(0);
}
else
{
/*if NOT co-clock:*/
/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) VCN28_ON_CTRL 0x041C[14] 1'b1*/
mt6325_upmu_set_rg_vcn28_on_ctrl(1);
/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)" RG_VCN28_EN" 0x041C[12] 1'b1 */
hwPowerOn(MT6325_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
}
#endif
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)"*/
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG, (CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
/*turn on top clock gating enable TOP_CLKCG_CLR 0x10000084[26] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP_CLKCG_CLR_REG,CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG) | CONSYS_TOP_CLKCG_BIT);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
#if PWR_ON_OFF_API_AVALIABLE
iRet = conn_power_on(); //consult clkmgr owner
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_on ok\n");
}
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)));
/*4.write conn_top1_mem_PD=0, power on MCU memory (MT6572 with the same addr) sram_conn_pd 0x10006280 [8] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SRAM_CONN_PD_BIT);
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on_s 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack_s 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)));
/*9.release connsys ISO, conn_top1_iso_en=0 (MT6572 with the same addr) conn_spm_pwr_iso 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 (MT6572 with the same addr) conn_spm_pwr_rst_b 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
#endif
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
/*11.26M is ready now, delay 10us for mem_pd de-assert*/
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++??*/
/*12.poll CONNSYS CHIP ID until 6580 is returned 0x18070008 32'h6752 */
while (retry-- > 0)
{
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)",CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if(consysHwChipId == 0x6580)
{
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
break;
}
msleep(20);
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 "[3:0] ROM DELSEL [7:$] RAM4Kx32 DELSEL" ??*/
/*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST (default write "1") ACR 0x18070110[18] 1'b1*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG, CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*update ANA_WBG(AFE) CR. AFE setting file: MT6752_AFE_SW_patch_REG_xxxx.xlsx ??" AP Offset = 0x180B2000 ??*/
#if 0
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset (need to check MT6580) 0x10007018 "[12]=1'b0 [31:24] =8'h88 (key)"*/
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
msleep(5);
}else{
#if PWR_ON_OFF_API_AVALIABLE
WMT_PLAT_INFO_FUNC("\n conn_power_off begin\n");
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off();//consult clkmgr owner
WMT_PLAT_INFO_FUNC("\n conn_power_off end\n");
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_off ok\n");
}
#else
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 (MT6572 with the same addr) 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
/*release connsys ISO, conn_top1_iso_en=1 (MT6572 with the same addr) 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
/*DA_WBG_EN_XBUF=0 */
/*wait 1us */
udelay(1);
/*write conn_top1_mem_PD=1, power off MCU memory (MT6572 with the same addr) 0x10006280 [8] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SRAM_CONN_PD_BIT);
/*write conn_top1_pwr_on=0, power off conn_top1 (MT6572 with the same addr) 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
/*write conn_clk_dis=1, disable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) |CONSYS_CLK_CTRL_BIT);
#endif
#if CONSYS_PMIC_CTRL_ENABLE
/*set VCN_28 to SW control mode (with PMIC_WRAP API) "1. VCN28_ON_CTRL "0x041C[14] 1'b0*/
mt6325_upmu_set_rg_vcn28_on_ctrl(0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" 2. RG_VCN28_EN" 0x041C[12]" 1'b0*/
hwPowerDown(MT6325_POWER_LDO_VCN28, "wcn_drv");
/*AP power off MT6625L VCN_1V8 LDO (with PMIC_WRAP API) "0x0512[1]1'b0 0x0512[14]" 1'b0*/
mt6325_upmu_set_rg_vcn18_mode_set(0);
hwPowerDown(MT6325_POWER_LDO_VCN18, "wcn_drv");
#endif
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol before 1/18/2013*/
/*1.Power on MT6323 VCN_1V8 LDO<--<VCN_1V8>-->write 0 to 0x512[1], write 1 to 0x512[14]*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN_1V8,VOL_DEFAULT,"MOD_WMT");
if(co_clock_en)
{
/*2.set VCN_28 to SW control mode<--<VCN28_ON_CTRL>-->write 0 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(0);
}
else
{
/*2.1.switch VCN28 to HW control mode<--<VCN28_ON_CTRL>-->write 1 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(1);
/*2.2.turn on VCN28LDO<--<RG_VCN28_EN>-->write 1 to 0x41C[12]*/
//upmu_set_rg_vcn28_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN28,VOL_DEFAULT,"MOD_WMT");
}
#endif
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*1.assert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b1, [31:24]=8'h88(key)--> CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY*/
CONSYS_SET_BIT(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
WMT_PLAT_DBG_FUNC("reg uump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
#endif
#if 0
/*turn on top clock gating enable*/
CONSYS_REG_WRITE(CONSYS_TOP_CLKCG_CLR_REG,CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG) | CONSYS_TOP_CLKCG_BIT);
WMT_PLAT_DBG_FUNC("reg dump:CONSYS_TOP_CLKCG_CLR_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG));
/*turn on SPM clock gating enable*/
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
WMT_PLAT_DBG_FUNC("reg dump:CONSYS_PWRON_CONFG_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWRON_CONFG_EN_REG));
#endif
/*use colck manger API to control MTCMOS*/
conn_power_on();
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
/*11.delay 10us, 26M is ready*/
udelay(10);
enable_clock(MT_CG_INFRA_CONNMCU, "WMT_MOD");
/*12.poll CONSYS CHIP until MT6582/MT6572 is returned, <CONSYS_CHIP_ID_REG>, 32'h6582/32'h6572 */
/*what does HW do, why we need to polling this register?*/
while (retry-- > 0)
{
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)",CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if((consysHwChipId == 0x6582) || (consysHwChipId == 0x6572))
{
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
break;
}
msleep(20);
}
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed, <CONSYS_ROM_RAM_DELSEL_REG>*/
/*14.write 1 to conn_mcu_config ACR[1] if real speed MBIST (default write "1"), <CONSYS_MCU_CFG_ACR_REG>,[18]1'b1-->CONSYS_MCU_CFG_ACR_MBIST_BIT*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_SET_BIT(CONSYS_MCU_CFG_ACR_REG, CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
/*16.deassert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b0, [31:24]=8'h88(key)*/
CONSYS_CLR_BIT_WITH_KEY(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT , CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(5);
iRet = 0;
}else{
disable_clock(MT_CG_INFRA_CONNMCU, "WMT_MOD");
/*New: use colck manger API to control MTCMOS*/
conn_power_off();
#if CONSYS_PMIC_CTRL_ENABLE
/*set VCN_28 to SW control mode*/
upmu_set_vcn28_on_ctrl(0);
/*turn off VCN28 LDO*/
//upmu_set_rg_vcn28_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN28,"MOD_WMT");
/*power off MT6627 VWCN_1V8 LDO*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN_1V8,"MOD_WMT");
#endif
iRet = 0;
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return iRet;
}
static INT32 wmt_plat_dump_pin_conf(VOID)
{
WMT_PLAT_DBG_FUNC("[WMT-PLAT]=>dump wmt pin configuration start<=\n");
#if defined(CONFIG_MTK_GPIO_LEGACY)
#ifdef GPIO_COMBO_BGF_EINT_PIN
WMT_PLAT_DBG_FUNC("BGF_EINT(GPIO%d)\n", GPIO_COMBO_BGF_EINT_PIN);
#else
WMT_PLAT_DBG_FUNC("BGF_EINT(not defined)\n");
#endif
#ifdef CUST_EINT_COMBO_BGF_NUM
WMT_PLAT_DBG_FUNC("BGF_EINT_NUM(%d)\n", CUST_EINT_COMBO_BGF_NUM);
#else
WMT_PLAT_DBG_FUNC("BGF_EINT_NUM(not defined)\n");
#endif
#ifdef GPIO_COMBO_URXD_PIN
WMT_PLAT_DBG_FUNC("UART_RX(GPIO%d)\n", GPIO_COMBO_URXD_PIN);
#else
WMT_PLAT_DBG_FUNC("UART_RX(not defined)\n");
#endif
#if defined(FM_DIGITAL_INPUT) || defined(FM_DIGITAL_OUTPUT)
#ifdef GPIO_COMBO_I2S_CK_PIN
WMT_PLAT_DBG_FUNC("I2S_CK(GPIO%d)\n", GPIO_COMBO_I2S_CK_PIN);
#else
WMT_PLAT_DBG_FUNC("I2S_CK(not defined)\n");
#endif
#ifdef GPIO_COMBO_I2S_WS_PIN
WMT_PLAT_DBG_FUNC("I2S_WS(GPIO%d)\n", GPIO_COMBO_I2S_WS_PIN);
#else
WMT_PLAT_DBG_FUNC("I2S_WS(not defined)\n");
#endif
#ifdef GPIO_COMBO_I2S_DAT_PIN
WMT_PLAT_DBG_FUNC("I2S_DAT(GPIO%d)\n", GPIO_COMBO_I2S_DAT_PIN);
#else
WMT_PLAT_DBG_FUNC("I2S_DAT(not defined)\n");
#endif
#else /* FM_ANALOG_INPUT || FM_ANALOG_OUTPUT */
WMT_PLAT_DBG_FUNC("FM digital mode is not set, no need for I2S GPIOs\n");
#endif
#ifdef GPIO_GPS_SYNC_PIN
WMT_PLAT_DBG_FUNC("GPS_SYNC(GPIO%d)\n", GPIO_GPS_SYNC_PIN);
#else
WMT_PLAT_DBG_FUNC("GPS_SYNC(not defined)\n");
#endif
#ifdef GPIO_GPS_LNA_PIN
WMT_PLAT_INFO_FUNC("GPS_LNA(GPIO%d)\n", GPIO_GPS_LNA_PIN);
#else
WMT_PLAT_INFO_FUNC("GPS_LNA(not defined)\n");
#endif
#else /* #if defined(CONFIG_MTK_GPIO_LEGACY) */
#endif
WMT_PLAT_DBG_FUNC("[WMT-PLAT]=>dump wmt pin configuration emds<=\n");
return 0;
}
