void main(void)
{
// main entry point
_DISABLE_COP();
/********************************************************************/
// initializations
/********************************************************************/
IIC0_Init();
for (;;)
{
WriteDAC(0b00100000,0b00110000,0x0FFF);
}
}
void
Timer0A_Handler(void) {
// Acknowledge that interrupt is processed.
Timer0->GPTMICR = 0x1UL;
if (currentCount > 0) {
WriteDAC(sound[currentWaveIndex]);
currentWaveIndex = currentWaveIndex + 1;
currentCount = currentCount - 1;
} else if (armedViaADC == 0 && ReadADC0() > 3000UL) {
armedViaADC = 1;
currentWaveIndex = 0;
currentCount = 4080;
} else if (armedViaADC == 1 && ReadADC0() < 3000UL) {
armedViaADC = 0;
}
}
VOID
P91Bt489RestoreMode(
PHW_DEVICE_EXTENSION HwDeviceExtension
)
/*++
routine description:
Restore the DAC to its pristine state.
arguments:
hwdeviceextension - pointer to the miniport driver's device extension.
return value:
--*/
{
UCHAR ucCurState;
VideoDebugPrint((0, "P91Bt489RestoreMode----------\n"));
//
// Enable accesses to CMD_REG_3. For the Power 9100, to access command
// register 3, you must have CR07 TRUE and you must load a one into
// the address register.
//
if (IS_DEV_P9100)
{
// Added per code received from R. Embry
WriteDAC(HwDeviceExtension, CMD_REG_0, ENB_CMD_REG_3);
P9_WR_REG(P9100_RAMWRITE, 0x02);
WR_CMD_REG_3(0x00);
// end added code
P9_WR_REG(P9100_RAMWRITE, 0x01);
WriteDAC(HwDeviceExtension, CMD_REG_0, ENB_CMD_REG_3);
// ucCurState = ReadDAC(HwDeviceExtension, CMD_REG_1);
// ucCurState = ReadDAC(HwDeviceExtension, CMD_REG_2);
// RD_CMD_REG_3(ucCurState);
// RD_CMD_REG_4(ucCurState);
WR_CMD_REG_4(0x00); // zero out cmd reg 4 on Bt489
WriteDAC(HwDeviceExtension, CMD_REG_0, 0x00);
WriteDAC(HwDeviceExtension, CMD_REG_1, 0x00);
WriteDAC(HwDeviceExtension, CMD_REG_2, 0x00);
return;
}
WriteDAC(HwDeviceExtension, CMD_REG_0, ENB_CMD_REG_3);
//
// Set pixel port for 8bit pixels.
//
WriteDAC(HwDeviceExtension, CMD_REG_1, PIX_PORT_8);
//
// Select VGA video clock, disable cursor.
//
WriteDAC(HwDeviceExtension, (ULONG) CMD_REG_2,
(UCHAR)(ReadDAC(HwDeviceExtension, (ULONG) CMD_REG_2) & DIS_CURS));
//
// Select 32x32 cursor, clear clock doubler bit.
//
RD_CMD_REG_3(ucCurState);
WR_CMD_REG_3(ucCurState & (~(DAC_CLK_2X | DAC_CLK_2X_489) & CUR_MODE_32));
//
// Set pixel read mask.
//
WriteDAC(HwDeviceExtension, PIXEL_MSK_REG, 0xff);
return;
}
BOOLEAN
P91Bt489SetMode(
PHW_DEVICE_EXTENSION HwDeviceExtension
)
/*++
Routine Description:
Initializes the DAC for the current mode.
Arguments:
HwDeviceExtension - Pointer to the miniport driver's device extension.
Return Value:
None.
--*/
{
USHORT usLoadClock;
UCHAR ucCurState;
VideoDebugPrint((0, "P91Bt489SetMode----------\n"));
// Added per code received from R. Embry
WriteDAC(HwDeviceExtension, PIXEL_MSK_REG, 0xff);
//
// Enable 8bit dacs, allow access to Command Register 3.
//
//
// Enable accesses to CMD_REG_3. For the Power 9100, to access command
// register 3, you must have CR07 TRUE and you must load a one into
// the address register.
//
if (IS_DEV_P9100)
P9_WR_REG(P9100_RAMWRITE, 0x01);
WriteDAC(HwDeviceExtension, CMD_REG_0, ENB_CMD_REG_3 | MODE_8_BIT);
//
// Set the DAC Pixel port value for the current bit depth.
// Note: The BT485 does not support 24bpp mode.
//
switch (HwDeviceExtension->usBitsPixel)
{
case 8:
WriteDAC(HwDeviceExtension, CMD_REG_1, PIX_PORT_8);
WR_CMD_REG_4( CR4_MUX_81 );
break;
case 16: // This is really 555, not 565...
WriteDAC(HwDeviceExtension, CMD_REG_1, PIX_PORT_15);
WR_CMD_REG_4( CR4_MUX_41 );
break;
case 24:
WriteDAC(HwDeviceExtension, CMD_REG_1, PIX_PORT_32);
WR_CMD_REG_4(CR4_MUX_24BPP);
break;
case 32:
WriteDAC(HwDeviceExtension, CMD_REG_1, PIX_PORT_32);
WR_CMD_REG_4( CR4_MUX_21 );
break;
default:
//
// Oops..invalid BPP value. Use 8BPP value for now.
//
WriteDAC(HwDeviceExtension, CMD_REG_1, PIX_PORT_8);
WR_CMD_REG_4( CR4_MUX_81 );
break;
};
// This code added per R. Embry from ECR 2/95
usLoadClock = (USHORT) ((HwDeviceExtension->VideoData.dotfreq1 /
HwDeviceExtension->Dac.usRamdacWidth) *
HwDeviceExtension->usBitsPixel);
if ( usLoadClock > 4850 )
{
ucCurState = SCLK_INV; // Bt489 - invert SCLK if in forbidden region
}
else
{
ucCurState = 0;
}
//
// Select P9x00 video clock, disable cursor
//
WriteDAC( HwDeviceExtension, CMD_REG_2,
(UCHAR)(ucCurState | ((PORTSEL_MSKD | PCLK1_SEL) & DIS_CURS)) );
//
// Select 32x32x2 cursor mode, and clock doubler mode if neccessary.
//
RD_CMD_REG_3(ucCurState);
if (HwDeviceExtension->VideoData.dotfreq1 >
HwDeviceExtension->Dac.ulMaxClkFreq)
{
//
// Enable the DAC clock doubler mode.
//
HwDeviceExtension->Dac.DACSetClkDblMode(HwDeviceExtension);
}
else
{
//
// Disable the DAC clock doubler mode.
//
HwDeviceExtension->Dac.DACClrClkDblMode(HwDeviceExtension);
}
//
// Set the pixel read mask.
//
WriteDAC(HwDeviceExtension, PIXEL_MSK_REG, 0xff);
//
// Set cursor colors 1 and 2.
//
WriteDAC(HwDeviceExtension, CURS_CLR_ADDR, 1);
WriteDAC(HwDeviceExtension, CURS_CLR_DATA, 0x00);
WriteDAC(HwDeviceExtension, CURS_CLR_DATA, 0x00);
WriteDAC(HwDeviceExtension, CURS_CLR_DATA, 0x00);
WriteDAC(HwDeviceExtension, CURS_CLR_DATA, 0xFF);
WriteDAC(HwDeviceExtension, CURS_CLR_DATA, 0xFF);
WriteDAC(HwDeviceExtension, CURS_CLR_DATA, 0xFF);
return(TRUE);
}
