static DECLFW(UNLVRC7Write) {
switch (A & 0xF008) {
case 0x8000: prg[0] = V; Sync(); break;
case 0x8008: prg[1] = V; Sync(); break;
case 0x9000: prg[2] = V; Sync(); break;
case 0xa000: chr[0] = V; Sync(); break;
case 0xa008: chr[1] = V; Sync(); break;
case 0xb000: chr[2] = V; Sync(); break;
case 0xb008: chr[3] = V; Sync(); break;
case 0xc000: chr[4] = V; Sync(); break;
case 0xc008: chr[5] = V; Sync(); break;
case 0xd000: chr[6] = V; Sync(); break;
case 0xd008: chr[7] = V; Sync(); break;
case 0xe000: mirr = V; Sync(); break;
case 0xe008: IRQLatch = V; X6502_IRQEnd(FCEU_IQEXT); break;
case 0xf000:
IRQa = V & 2;
IRQd = V & 1;
if (V & 2)
IRQCount = IRQLatch;
CycleCount = 0;
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xf008:
if (IRQd)
IRQa = 1;
else
IRQa = 0;
X6502_IRQEnd(FCEU_IQEXT);
break;
}
}
static DECLFW(M91Write1)
{
switch (A & 3)
{
case 0:
case 1: pregs[A & 1] = V; Sync(); break;
case 2: IRQa = IRQCount = 0; X6502_IRQEnd(FCEU_IQEXT); break;
case 3: IRQa = 1; X6502_IRQEnd(FCEU_IQEXT); break;
}
}
static DECLFW(Mapper24_write)
{
if(swaparoo)
A=(A&0xFFFC)|((A>>1)&1)|((A<<1)&2);
if(A>=0x9000 && A<=0xb002)
{
VRC6SW(A,V);
return;
}
A&=0xF003;
// if(A>=0xF000) printf("%d, %d, $%04x:$%02x\n",scanline,timestamp,A,V);
switch(A&0xF003)
{
case 0x8000:ROM_BANK16(0x8000,V);break;
case 0xB003:
switch(V&0xF)
{
case 0x0:MIRROR_SET2(1);break;
case 0x4:MIRROR_SET2(0);break;
case 0x8:onemir(0);break;
case 0xC:onemir(1);break;
}
break;
case 0xC000:ROM_BANK8(0xC000,V);break;
case 0xD000:VROM_BANK1(0x0000,V);break;
case 0xD001:VROM_BANK1(0x0400,V);break;
case 0xD002:VROM_BANK1(0x0800,V);break;
case 0xD003:VROM_BANK1(0x0c00,V);break;
case 0xE000:VROM_BANK1(0x1000,V);break;
case 0xE001:VROM_BANK1(0x1400,V);break;
case 0xE002:VROM_BANK1(0x1800,V);break;
case 0xE003:VROM_BANK1(0x1c00,V);break;
case 0xF000:IRQLatch=V;
//acount=0;
break;
case 0xF001:IRQa=V&2;
vrctemp=V&1;
if(V&2)
{
IRQCount=IRQLatch;
acount=0;
}
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xf002:IRQa=vrctemp;
X6502_IRQEnd(FCEU_IQEXT);break;
case 0xF003:break;
}
}
static DECLFW(UNLKS7032Write)
{
// FCEU_printf("bs %04x %02x\n",A,V);
switch(A)
{
// case 0x8FFF: reg[4]=V; Sync(); break;
case 0x8000: X6502_IRQEnd(FCEU_IQEXT); IRQCount=(IRQCount&0x000F)|(V&0x0F); break;
case 0x9000: X6502_IRQEnd(FCEU_IQEXT); IRQCount=(IRQCount&0x00F0)|((V&0x0F)<<4); break;
case 0xA000: X6502_IRQEnd(FCEU_IQEXT); IRQCount=(IRQCount&0x0F00)|((V&0x0F)<<8); break;
case 0xB000: X6502_IRQEnd(FCEU_IQEXT); IRQCount=(IRQCount&0xF000)|(V<<12); break;
case 0xC000: X6502_IRQEnd(FCEU_IQEXT); IRQa=1; break;
case 0xE000: cmd=V&7; break;
case 0xF000: reg[cmd]=V; Sync(); break;
}
}
static DECLFW(M117Write) {
if (A < 0x8004) {
prgreg[A & 3] = V;
Sync();
} else if ((A >= 0xA000) && (A <= 0xA007)) {
chrreg[A & 7] = V;
Sync();
} else switch (A) {
case 0xc001: IRQLatch = V; break;
case 0xc003: IRQCount = IRQLatch; IRQa |= 2; break;
case 0xe000: IRQa &= ~1; IRQa |= V & 1; X6502_IRQEnd(FCEU_IQEXT); break;
case 0xc002: X6502_IRQEnd(FCEU_IQEXT); break;
case 0xd000: mirror = V & 1;
}
}
static DECLFW(LH53IRQaWrite)
{
IRQa = V&2;
IRQCount = 0;
if(!IRQa)
X6502_IRQEnd(FCEU_IQEXT);
}
static DECLFW(Mapper69_write)
{
switch(A&0xE000)
{
case 0x8000:reg_select=V;break;
case 0xa000:
reg_select&=0xF;
if(reg_select < 8)
{
CHRRegs[reg_select] = V;
SyncCHR();
}
else
switch(reg_select&0x0f)
{
case 0x8: wram_control = V; SyncPRG(); break;
case 0x9: PRGRegs[0] = V & 0x3F; SyncPRG(); break;
case 0xa: PRGRegs[1] = V & 0x3F; SyncPRG(); break;
case 0xb: PRGRegs[2] = V & 0x3F; SyncPRG(); break;
case 0xc: Mirroring = V & 0x3; SyncMirroring(); break;
case 0xd:IRQa=V; X6502_IRQEnd(MDFN_IQEXT); break;
case 0xe:IRQCount&=0xFF00;IRQCount|=V;break;
case 0xf:IRQCount&=0x00FF;IRQCount|=V<<8;break;
}
break;
}
}
static DECLFW(Mapper65_write)
{
//if(A>=0x9000 && A<=0x9006)
// printf("$%04x:$%02x, %d\n",A,V,scanline);
switch(A)
{
//default: printf("$%04x:$%02x\n",A,V);
// break;
case 0x8000:ROM_BANK8(0x8000,V);break;
// case 0x9000:printf("$%04x:$%02x\n",A,V);MIRROR_SET2((V>>6)&1);break;
case 0x9001:MIRROR_SET(V>>7);break;
case 0x9003:IRQa=V&0x80;X6502_IRQEnd(FCEU_IQEXT);break;
case 0x9004:IRQCount=IRQLatch;break;
case 0x9005: IRQLatch&=0x00FF;
IRQLatch|=V<<8;
break;
case 0x9006: IRQLatch&=0xFF00;IRQLatch|=V;
break;
case 0xB000:VROM_BANK1(0x0000,V);break;
case 0xB001:VROM_BANK1(0x0400,V);break;
case 0xB002:VROM_BANK1(0x0800,V);break;
case 0xB003:VROM_BANK1(0x0C00,V);break;
case 0xB004:VROM_BANK1(0x1000,V);break;
case 0xB005:VROM_BANK1(0x1400,V);break;
case 0xB006:VROM_BANK1(0x1800,V);break;
case 0xB007:VROM_BANK1(0x1C00,V);break;
case 0xa000:ROM_BANK8(0xA000,V);break;
case 0xC000:ROM_BANK8(0xC000,V);break;
}
//MIRROR_SET2(1);
}
static DECLFW(Mapper153_write)
{
A&=0xF;
if(A<=0x7)
{
mapbyte1[A&7]=V;
PRGO();
}
else if(A==0x8)
{
mapbyte2[0]=V;
PRGO();
}
else switch(A) {
case 0x9: switch(V&3) {
case 0x00:MIRROR_SET2(1);break;
case 0x01:MIRROR_SET2(0);break;
case 0x02:onemir(0);break;
case 0x03:onemir(1);break;
}
break;
case 0xA:X6502_IRQEnd(FCEU_IQEXT);
IRQa=V&1;
IRQCount=IRQLatch;
break;
case 0xB:IRQLatch&=0xFF00;
IRQLatch|=V;
break;
case 0xC:IRQLatch&=0xFF;
IRQLatch|=V<<8;
break;
}
}
static DECLFW(Mapper16_write)
{
A&=0xF;
if(A<=0x7)
VROM_BANK1(A<<10,V);
else if(A==0x8)
ROM_BANK16(0x8000,V);
else switch(A) {
case 0x9: switch(V&3) {
case 0x00:MIRROR_SET2(1);break;
case 0x01:MIRROR_SET2(0);break;
case 0x02:onemir(0);break;
case 0x03:onemir(1);break;
}
break;
case 0xA:X6502_IRQEnd(FCEU_IQEXT);
IRQa=V&1;
IRQCount=IRQLatch;
break;
case 0xB:IRQLatch&=0xFF00; IRQLatch|=V;
break;
case 0xC:IRQLatch&=0xFF; IRQLatch|=V<<8;
break;
case 0xD: break;/* Serial EEPROM control port */
}
}
static DECLFW(Write)
{
A &= 0xF003;
if((A & 0xF000) == 0x8000)
PRGBanks[0] = V;
else if((A & 0xF000) == 0xA000)
PRGBanks[1] = V;
else switch(A)
{
case 0xb000: CHRBanks[0] = V; break;
case 0xb002: CHRBanks[1] = V; break;
case 0xc000: CHRBanks[2] = V; break;
case 0xc002: CHRBanks[3] = V; break;
case 0xd000: CHRBanks[4] = V; break;
case 0xd002: CHRBanks[5] = V; break;
case 0xe000: CHRBanks[6] = V; break;
case 0xe002: CHRBanks[7] = V; break;
case 0xf000: IRQLatch = V; break;
case 0xf001: X6502_IRQEnd(MDFN_IQEXT); IRQa = 0; IRQCount = IRQLatch; break;
case 0xf002: IRQa = 1; break;
default: printf("%04x: %02x\n", A, V);break;
}
Sync();
}
static DECLFW(RAMBO1_write)
{
switch(A&0xF001)
{
case 0xa000: mir=V&1;
// if(!nomirror)
setmirror(mir^1);
break;
case 0x8000: cmd = V;
break;
case 0x8001: if((cmd&0xF)<10)
DRegs[cmd&0xF]=V;
else if((cmd&0xF)==0xF)
DRegs[10]=V;
Synco();
break;
case 0xc000: IRQLatch=V;
if(rmode==1)
IRQCount=IRQLatch;
break;
case 0xc001: rmode=1;
IRQCount=IRQLatch;
IRQmode=V&1;
break;
case 0xE000: IRQa=0;
X6502_IRQEnd(FCEU_IQEXT);
if(rmode==1)
IRQCount=IRQLatch;
break;
case 0xE001: IRQa=1;
if(rmode==1)
IRQCount=IRQLatch;
break;
}
}
static DECLFW(Mapper40_write)
{
switch(A&0xe000)
{
case 0x8000:IRQa=0;IRQCount=0;X6502_IRQEnd(FCEU_IQEXT);break;
case 0xa000:IRQa=1;break;
case 0xe000:ROM_BANK8(0xc000,V&7);break;
}
}
static DECLFW(M43Write)
{
int transo[8]={4,3,4,4,4,7,5,6};
switch(A&0xf1ff)
{
case 0x4022: reg=transo[V&7]; Sync(); break;
case 0x8122: IRQa=V&1; X6502_IRQEnd(FCEU_IQEXT); IRQCount=0; break;
}
}
static DECLFW(Mapper73_write)
{
//printf("$%04x:$%02x\n",A,V);
switch(A&0xF000)
{
case 0x8000:
IRQr&=0xFFF0;IRQr|=(V&0xF);
break;
case 0x9000:
IRQr&=0xFF0F;IRQr|=(V&0xF)<<4;
break;
case 0xa000:
IRQr&=0xF0FF;IRQr|=(V&0xF)<<8;
break;
case 0xb000:
IRQr&=0x0FFF;IRQr|=(V&0xF)<<12;
break;
case 0xc000:
IRQm=V&4;
IRQx=V&1;
IRQa=V&2;
if(IRQa)
{
if(IRQm)
{
IRQCount&=0xFFFF;
IRQCount|=(IRQr&0xFF);
}
else
{
IRQCount=IRQr;
}
}
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xd000:
X6502_IRQEnd(FCEU_IQEXT);
IRQa=IRQx;
break;
case 0xf000:ROM_BANK16(0x8000,V);break;
}
}
static DECLFW(M43Write) {
// int transo[8]={4,3,4,4,4,7,5,6};
int transo[8] = { 4, 3, 5, 3, 6, 3, 7, 3 }; // According to hardware tests
switch (A & 0xf1ff) {
case 0x4022: reg = transo[V & 7]; Sync(); break;
case 0x4120: swap = V & 1; Sync(); break;
case 0x8122: // hacked version
case 0x4122: IRQa = V & 1; X6502_IRQEnd(FCEU_IQEXT); IRQCount = 0; break; // original version
}
}
static DECLFW(M18WriteIRQ) {
switch (A & 0xF003) {
case 0xE000: IRQLatch &= 0xFFF0; IRQLatch |= (V & 0x0f) << 0x0; break;
case 0xE001: IRQLatch &= 0xFF0F; IRQLatch |= (V & 0x0f) << 0x4; break;
case 0xE002: IRQLatch &= 0xF0FF; IRQLatch |= (V & 0x0f) << 0x8; break;
case 0xE003: IRQLatch &= 0x0FFF; IRQLatch |= (V & 0x0f) << 0xC; break;
case 0xF000: IRQCount = IRQLatch; break;
case 0xF001: IRQa = V & 1; X6502_IRQEnd(FCEU_IQEXT); break;
case 0xF002: mirr = V & 3; Sync(); break;
}
}
static DECLFW(Mapper48_HiWrite)
{
switch(A&0xF003)
{
case 0xc000:IRQLatch=V;break;
case 0xc001:IRQCount=IRQLatch;break;
case 0xc003:IRQa=0;X6502_IRQEnd(FCEU_IQEXT);break;
case 0xc002:IRQa=1;break;
case 0xe000:MIRROR_SET((V>>6)&1);break;
}
}
static DECLFW(M106Write)
{
A&=0xF;
switch(A)
{
case 0xD: IRQa=0; IRQCount=0; X6502_IRQEnd(FCEU_IQEXT); break;
case 0xE: IRQCount=(IRQCount&0xFF00)|V; break;
case 0xF: IRQCount=(IRQCount&0x00FF)|(V<<8); IRQa=1; break;
default: reg[A]=V; Sync(); break;
}
}
static DECLFW(Mapper69_write)
{
switch(A&0xE000)
{
case 0x8000:sunselect=V;break;
case 0xa000:
sunselect&=0xF;
if(sunselect<=7)
VROM_BANK1(sunselect<<10,V);
else
switch(sunselect&0x0f)
{
case 8:
sungah=V;
if(V&0x40)
{
if(V&0x80) // Select WRAM
setprg8r(0x10,0x6000,0);
}
else
setprg8(0x6000,V);
break;
case 9:ROM_BANK8(0x8000,V);break;
case 0xa:ROM_BANK8(0xa000,V);break;
case 0xb:ROM_BANK8(0xc000,V);break;
case 0xc:
switch(V&3)
{
case 0:MIRROR_SET2(1);break;
case 1:MIRROR_SET2(0);break;
case 2:onemir(0);break;
case 3:onemir(1);break;
}
break;
case 0xd:IRQa=V;X6502_IRQEnd(FCEU_IQEXT);break;
case 0xe:IRQCount&=0xFF00;IRQCount|=V;X6502_IRQEnd(FCEU_IQEXT);break;
case 0xf:IRQCount&=0x00FF;IRQCount|=V<<8;X6502_IRQEnd(FCEU_IQEXT);break;
}
break;
}
}
static DECLFW(UNL3DBlockWrite) {
switch (A) {
//4800 32
//4900 37
//4a00 01
//4e00 18
case 0x4800: reg[0] = V; break;
case 0x4900: reg[1] = V; break;
case 0x4a00: reg[2] = V; break;
case 0x4e00: reg[3] = V; IRQCount = Count; IRQPause = Pause; IRQa = 1; X6502_IRQEnd(FCEU_IQEXT); break;
}
}
static void NWCCHRHook(uint32 A, uint8 V)
{
if((V&0x10)) // && !(NWCRec&0x10))
{
NWCIRQCount=0;
X6502_IRQEnd(MDFN_IQEXT);
}
NWCRec=V;
if(V&0x08)
MMC1PRG();
else
setprg32(0x8000,(V>>1)&3);
}
static DECLFW(UNLSMB2JWrite)
{
if(A==0x4022)
{
prg=V&1;
Sync();
}
if(A==0x4122)
{
IRQa=V;
IRQCount=0;
X6502_IRQEnd(FCEU_IQEXT);
}
}
static DECLFW(M73Write) {
switch (A & 0xF000) {
case 0x8000: IRQReload &= 0xFFF0; IRQReload |= (V & 0xF) << 0; break;
case 0x9000: IRQReload &= 0xFF0F; IRQReload |= (V & 0xF) << 4; break;
case 0xA000: IRQReload &= 0xF0FF; IRQReload |= (V & 0xF) << 8; break;
case 0xB000: IRQReload &= 0x0FFF; IRQReload |= (V & 0xF) << 12; break;
case 0xC000:
IRQm = V & 4;
IRQx = V & 1;
IRQa = V & 2;
if (IRQa) {
if (IRQm) {
IRQCount &= 0xFFFF;
IRQCount |= (IRQReload & 0xFF);
} else
IRQCount = IRQReload;
}
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xD000: X6502_IRQEnd(FCEU_IQEXT); IRQa = IRQx; break;
case 0xF000: preg = V; Sync(); break;
}
}
static DECLFR(UNLSB2000Read) {
switch(A) {
case 0x4033: // IRQ flags
X6502_IRQEnd(FCEU_IQFCOUNT);
return 0xff;
// case 0x4204: // unk
// return 0xff;
// case 0x4205: // unk
// return 0xff;
default:
FCEU_PrintFatalError("unk read: %04x caused end of function to be reached (%s:%d)\n",A, __FILE__, __LINE__);
// break;
return 0xff; // needed to prevent C4715 warning?
}
}
static DECLFR(FDSRead4031)
{
static uint8 z=0;
if(ActiveDisk >= 0)
{
z=diskdata[ActiveDisk][DiskPtr];
if(!fceuindbg)
{
if(DiskPtr<64999) DiskPtr++;
DiskSeekIRQ=150;
X6502_IRQEnd(MDFN_IQEXT2);
}
}
return z;
}
static void UNL3DBlockIRQHook(int a) {
if (IRQa) {
if (IRQCount > 0) {
IRQCount -= a;
} else {
if (IRQPause > 0) {
IRQPause -= a;
X6502_IRQBegin(FCEU_IQEXT);
} else {
IRQCount = Count;
IRQPause = Pause;
X6502_IRQEnd(FCEU_IQEXT);
}
}
}
}
static DECLFW(BandaiWrite)
{
A&=0x0F;
if(A<0x0A)
{
reg[A&0x0F]=V;
BandaiSync();
}
else
switch(A)
{
case 0x0A: X6502_IRQEnd(FCEU_IQEXT); IRQa=V&1; IRQCount=IRQLatch; break;
case 0x0B: IRQLatch&=0xFF00; IRQLatch|=V; break;
case 0x0C: IRQLatch&=0xFF; IRQLatch|=V<<8; break;
case 0x0D: break;// Serial EEPROM control port
}
}
static DECLFW(M50W)
{
if((A&0xD060)==0x4020)
{
if(A&0x100)
{
IRQa=V&1;
if(!IRQa) IRQCount=0;
X6502_IRQEnd(FCEU_IQEXT);
}
else
{
V=((V&1)<<2)|((V&2)>>1)|((V&4)>>1)|(V&8);
mapbyte1[0]=V;
setprg8(0xc000,V);
}
}
}
static DECLFW(UNLSC127Write) {
switch (A) {
case 0x8000: reg[0] = V; break;
case 0x8001: reg[1] = V; break;
case 0x8002: reg[2] = V; break;
case 0x9000: chr[0] = V; break;
case 0x9001: chr[1] = V; break;
case 0x9002: chr[2] = V; break;
case 0x9003: chr[3] = V; break;
case 0x9004: chr[4] = V; break;
case 0x9005: chr[5] = V; break;
case 0x9006: chr[6] = V; break;
case 0x9007: chr[7] = V; break;
case 0xC002: IRQa = 0; X6502_IRQEnd(FCEU_IQEXT); break;
case 0xC005: IRQCount = V; break;
case 0xC003: IRQa = 1; break;
case 0xD001: reg[3] = V; break;
}
Sync();
}
