Esempio n. 1
0
/**
*
* Sends a CAPTURE command to the ICAP port.  This command captures all
* of the flip flop states so they will be available during readback.
* One can use this command instead of enabling the CAPTURE block in the
* design.
*
* @param	InstancePtr is a pointer to the XHwIcap instance.
*
* @return	XST_SUCCESS or XST_FAILURE
*
* @note		None.
*
*****************************************************************************/
int XHwIcap_CommandCapture(XHwIcap *InstancePtr)
{
	int Status;
	u32 FrameBuffer[CAPTURE_COMMAND_SIZE];
	u32 Index =0;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Create the data to be written to the ICAP.
	 */
	FrameBuffer[Index++] = XHI_DUMMY_PACKET;
	FrameBuffer[Index++] = XHI_SYNC_PACKET;
#if ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) \
	|| (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES ))
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
#endif
	FrameBuffer[Index++] = (XHwIcap_Type1Write(XHI_CMD) | 1);
	FrameBuffer[Index++] = XHI_CMD_GCAPTURE;
	FrameBuffer[Index++] =  XHI_DUMMY_PACKET;
	FrameBuffer[Index++] =  XHI_DUMMY_PACKET;

	/*
	 * Write the data to the FIFO and intiate the transfer of data present
	 * in the FIFO to the ICAP device.
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, &FrameBuffer[0], Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	return XST_SUCCESS;
}
Esempio n. 2
0
/**
*
* Sends a DESYNC command to the ICAP port.
*
* @param	InstancePtr - a pointer to the XHwIcap instance to be worked on
*
* @return	XST_SUCCESS else XST_FAILURE
*
* @note		None.
*
******************************************************************************/
int XHwIcap_CommandDesync(XHwIcap *InstancePtr)
{
	int Status;
#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
	u16 FrameBuffer[DESYNC_COMMAND_SIZE];
#else
	u32 FrameBuffer[DESYNC_COMMAND_SIZE];
#endif
	u32 Index =0;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Create the data to be written to the ICAP.
	 */
	FrameBuffer[Index++] = (XHwIcap_Type1Write(XHI_CMD) | 1);
	FrameBuffer[Index++] = XHI_CMD_DESYNCH;
	FrameBuffer[Index++] = XHI_DUMMY_PACKET;
	FrameBuffer[Index++] = XHI_DUMMY_PACKET;


	/*
	 * Write the data to the FIFO and intiate the transfer of data present
	 * in the FIFO to the ICAP device.
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, &FrameBuffer[0], Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	return XST_SUCCESS;
}
Esempio n. 3
0
///
/// Load a bitstream via ICAP
///
/// @param bitstream pointer to the bitstream array
/// @param length    length of bitstream in bytes
///
void icap_load(unsigned char * bitstream, size_t length){

        XStatus status;

        if (!cyg_mutex_lock(&icap_mutex)) {
            CYG_FAIL("mutex lock failed, aborting thread\n");
        } else {

            // wait until ICAP is ready
            while (HwIcap.IsTransferInProgress) {
                diag_printf("icap_load(): transfer in progress, waiting...\n");
                cyg_thread_delay(1);
            }
            while (! (XHwIcap_GetStatusReg(&HwIcap) & XHI_SR_DONE_MASK)) {
                diag_printf("icap_load(): device busy, waiting...\n");
                cyg_thread_delay(1);
            }

            status = XHwIcap_DeviceWrite(&HwIcap, (Xuint32*)bitstream, length/4);
            if (status != XST_SUCCESS)
            {
                if(status == XST_DEVICE_BUSY) diag_printf("HWICAP: device busy\n");
                if(status == XST_INVALID_PARAM) diag_printf("HWICAP: invalid parameter\n");
                CYG_FAIL("failed to load bitstream\naborting\n");
            }

            // wait until ICAP is ready
            while (HwIcap.IsTransferInProgress) {
                diag_printf("icap_load(): transfer in progress, waiting...\n");
                cyg_thread_delay(1);
            }
            while (! (XHwIcap_GetStatusReg(&HwIcap) & XHI_SR_DONE_MASK)) {
                diag_printf("icap_load(): device busy, waiting...\n");
                cyg_thread_delay(1);
            }

            cyg_mutex_unlock(&icap_mutex);
        }
}
Esempio n. 4
0
/**
 *
 * This function returns the value of the specified configuration register.
 *
 * @param	InstancePtr is a pointer to the XHwIcap instance.
 * @param	ConfigReg  is a constant which represents the configuration
 *		register value to be returned. Constants specified in
 *		xhwicap_i.h.
 * 		Examples:  XHI_IDCODE, XHI_FLR.
 * @param	RegData is the value of the specified configuration
 *		register.
 *
 * @return	XST_SUCCESS or XST_FAILURE
 *
 * @note	This is a blocking call.
 *
 *****************************************************************************/
u32 XHwIcap_GetConfigReg(XHwIcap *InstancePtr, u32 ConfigReg, u32 *RegData)
{
	int Status;
	int EosRetries =0; /* Counter for checking EOS to become high */

#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
	u16 FrameBuffer[READ_CFG_REG_COMMAND_SIZE];
	u32 Retries =0;
#else
	u32 FrameBuffer[READ_CFG_REG_COMMAND_SIZE];
#endif
	u32 Index =0;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Create the data to be written to the ICAP.
	 */
	FrameBuffer[Index++] = XHI_DUMMY_PACKET;

#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
	FrameBuffer[Index++] = XHI_SYNC_PACKET1;
	FrameBuffer[Index++] = XHI_SYNC_PACKET2;
#else
	FrameBuffer[Index++] = XHI_SYNC_PACKET;
#endif
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;

#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
	if (ConfigReg == XHI_IDCODE) {
		FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x2;
	}else {
		FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x1;
	}
#else
	FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x1;
#endif

	FrameBuffer[Index++] = XHI_NOOP_PACKET;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Check for EOS bit of Status Register. EOS bit becomes high after
	 * ICAP completes Start up sequence. Access to ICAP should start
	 * only after EOS bit becomes high.
	 */

	while((!(XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
			XHI_SR_OFFSET)& XHI_SR_EOS_MASK))) {

		if(EosRetries < XHI_MAX_RETRIES) {
			EosRetries++;
		}
		else {
	   		return XST_FAILURE;
		}

	}

	/*
	 * Write the data to the FIFO and intiate the transfer of data present
	 * in the FIFO to the ICAP device.
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, &FrameBuffer[0], Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE);
	while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
			XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);

#if (XHI_FAMILY == XHI_DEV_FAMILY_V6) ||\
(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)

	/*
	 * Read the Config Register using DeviceRead since
	 * DeviceRead reads depending on ICAP Width for V6
	 * and 7 series devices
  	 */
	XHwIcap_DeviceRead(InstancePtr, RegData, 1);

#else

	XHwIcap_SetSizeReg(InstancePtr, 1);

	if (ConfigReg == XHI_IDCODE) {
		XHwIcap_SetSizeReg(InstancePtr, 2);
	}

	XHwIcap_StartReadBack(InstancePtr);
	while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE) {
		Retries++;
		if (Retries > XHI_MAX_RETRIES) {
			return XST_FAILURE;
		}
	}
	while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
						XHI_CR_OFFSET)) &
						XHI_CR_READ_MASK);

	/*
	 * Return the Register value
	 */
	*RegData = XHwIcap_FifoRead(InstancePtr);

	if (ConfigReg == XHI_IDCODE) {

		*RegData = ((*RegData << 16) |
						(XHwIcap_FifoRead(InstancePtr)));
	}

#endif
	return XST_SUCCESS;
}
/**
*
* Writes one frame from the specified buffer and puts it in the device
* (ICAP).
*
* @param	InstancePtr is a pointer to the XHwIcap instance.
* @param	Top - top (0) or bottom (1) half of device
* @param	Block - Block Address (XHI_FAR_CLB_BLOCK,
* 		XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
* @param	HClkRow - selects the HClk Row
* @param	MajorFrame - selects the column
* @param	MinorFrame - selects frame inside column
* @param	FrameData is a pointer to the frame that is to be written
*		to the device.
*
* @return	XST_SUCCESS else XST_FAILURE.
*
* @note		This is a blocking function.
*		This function is used in conjunction with the function
*		XHwIcap_DeviceReadFrame. This function is used to write back
*		the frame of data read using the XHwIcap_DeviceReadFrame.
*
*****************************************************************************/
int XHwIcap_DeviceWriteFrame(XHwIcap *InstancePtr, long Top, long Block,
				long HClkRow, long MajorFrame, long MinorFrame,
				u32 *FrameData)
{

	u32 Packet;
	u32 Data;
	u32 TotalWords;
	int Status;
	u32 WriteBuffer[READ_FRAME_SIZE];
	u32 Index =0;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid(FrameData != NULL);


	/*
	 * DUMMY and SYNC
	 */
	WriteBuffer[Index++] = XHI_DUMMY_PACKET;
	WriteBuffer[Index++] = XHI_SYNC_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Reset CRC
	 */
	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
	Data = XHI_CMD_RCRC;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;



	/*
	 * Bypass CRC
	 */
#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
	Packet = XHwIcap_Type1Write(XHI_COR) | 1;
	Data = 0x10042FDD;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;
#endif
	/*
	 * ID register
	 */
	Packet = XHwIcap_Type1Write(XHI_IDCODE) | 1;
	Data = InstancePtr->DeviceIdCode;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;


	/*
	 * Setup FAR
	 */
	Packet = XHwIcap_Type1Write(XHI_FAR) | 1;
#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex 4 */
	Data = XHwIcap_SetupFarV4(Top, Block, HClkRow,  MajorFrame, MinorFrame);
#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
	(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
	Data = XHwIcap_SetupFarV5(Top, Block, HClkRow,  MajorFrame, MinorFrame);
#endif

	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;

	/*
	 * Setup CMD register - write configuration
	 */
	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
	Data = XHI_CMD_WCFG;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Setup Packet header.
	 */
	TotalWords = InstancePtr->WordsPerFrame << 1;
	if (TotalWords < XHI_TYPE_1_PACKET_MAX_WORDS)  {
		/*
		 * Create Type 1 Packet.
		 */
		Packet = XHwIcap_Type1Write(XHI_FDRI) | TotalWords;
		WriteBuffer[Index++] = Packet;
	}
	else {

		/*
		 * Create Type 2 Packet.
		 */
		Packet = XHwIcap_Type1Write(XHI_FDRI);
		WriteBuffer[Index++] = Packet;

		Packet = XHI_TYPE_2_WRITE | TotalWords;
		WriteBuffer[Index++] = Packet;
	}


	/*
	 * Write the Header data into the FIFO and intiate the transfer of
	 * data present in the FIFO to the ICAP device
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, (u32 *)&WriteBuffer[0], Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	/*
	 * Write the modified frame data.
	 */
#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
	Status = XHwIcap_DeviceWrite(InstancePtr,
				(u32 *) &FrameData[InstancePtr->WordsPerFrame + 1],
				InstancePtr->WordsPerFrame);
#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)) /* Virtex 6 */
	Status = XHwIcap_DeviceWrite(InstancePtr,
				(u32 *) &FrameData[InstancePtr->WordsPerFrame],
				InstancePtr->WordsPerFrame);
#endif
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Write out the pad frame. The pad frame was read from the device
	 * before the data frame.
	 */

#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
	Status = XHwIcap_DeviceWrite(InstancePtr, (u32 *) &FrameData[1],
				    InstancePtr->WordsPerFrame);
#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)) /* Virtex6 */
	Status = XHwIcap_DeviceWrite(InstancePtr, (u32 *) &FrameData[0],
				    InstancePtr->WordsPerFrame);
#endif
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/* Add CRC */
	Index = 0;
#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
	Packet = XHwIcap_Type1Write(XHI_CRC) | 1;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = XHI_DISABLED_AUTO_CRC;
#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)) /* Virtex6 */
	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
	Data = XHI_CMD_RCRC;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
#endif

	/* Park the FAR */
	Packet = XHwIcap_Type1Write(XHI_FAR) | 1;

#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
	Data = XHwIcap_SetupFarV4(0, 0, 3, 33, 0);
#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
	(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
	Data = XHwIcap_SetupFarV5(0, 0, 3, 33, 0);
#endif

	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] =  Data;

	/* Add CRC */
#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
	Packet = XHwIcap_Type1Write(XHI_CRC) | 1;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = XHI_DISABLED_AUTO_CRC;
#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)) /* Virtex6 */
	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
	Data = XHI_CMD_RCRC;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
#endif

	/*
	 * Intiate the transfer of data present in the FIFO to
	 * the ICAP device
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, &WriteBuffer[0], Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	/*
	 * Send DESYNC command
	 */
	Status = XHwIcap_CommandDesync(InstancePtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	return XST_SUCCESS;
};
/**
*
* Writes one frame from the specified buffer and puts it in the device
* (ICAP).
*
* @param	InstancePtr is a pointer to the XHwIcap instance.
* @param	Top - top (0) or bottom (1) half of device
* @param	Block - Block Address (XHI_FAR_CLB_BLOCK,
* 		XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
* @param	HClkRow - selects the HClk Row
* @param	MajorFrame - selects the column
* @param	MinorFrame - selects frame inside column
* @param	FrameData is a pointer to the frame that is to be written
*		to the device.
*
* @return	XST_SUCCESS else XST_FAILURE.
*
* @note		This is a blocking function.
*		This function is used in conjunction with the function
*		XHwIcap_DeviceReadFrame. This function is used to write back
*		the frame of data read using the XHwIcap_DeviceReadFrame.
*
*****************************************************************************/
int XHwIcap_DeviceWriteFrame(XHwIcap *InstancePtr, long Block, long Row,
				long MajorFrame, long MinorFrame,
				u16 *FrameData)
{
	u16 Packet;
	u16 TotalWords;
	int Status;
	u16 WriteBuffer[READ_FRAME_SIZE];
	u16 Data;
	u16 Index =0;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid(FrameData != NULL);

	/*
	 * DUMMY and SYNC
	 */
	WriteBuffer[Index++] = XHI_DUMMY_PACKET;
	WriteBuffer[Index++] = XHI_SYNC_PACKET1;
	WriteBuffer[Index++] = XHI_SYNC_PACKET2;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Reset CRC
	 */
	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
	Data = XHI_CMD_RCRC;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;


	/*
	 * Write the FLR
	 */
	Packet = XHwIcap_Type1Write(XHI_FLR) | 1;
	WriteBuffer[Index++] =  Packet ;
	WriteBuffer[Index++] =  0x430;

	/*
	 * ID register
	 */
	Packet = XHwIcap_Type1Write(XHI_IDCODE) | 2;
	WriteBuffer[Index++] = Packet;

	/*
	 * It is written wrongly in the document that only lower 16 bits are
	 * needed.The document will be updated. We need the complete 32 bit.
	 */
	Data = (u16)(InstancePtr->DeviceIdCode >> 16);
	WriteBuffer[Index++] = Data;
	Data = (u16)InstancePtr->DeviceIdCode;
	WriteBuffer[Index++] = Data;

	/*
	 * Bypass CRC
	 */
	Packet = XHwIcap_Type1Write(XHI_COR1) | 1;
	Data = XHI_COR1_DEFAULT;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;


	Packet = XHwIcap_Type1Write(XHI_COR2) | 1;
	Data = XHI_COR2_DEFAULT;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;

	/*
	 * Write the FAR MAJ and MIN address values
	 */
	Packet = XHwIcap_Type1Write(XHI_FAR_MAJ) | 1;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = (Block << XHI_BLOCK_SHIFT) |
				(Row << XHI_ROW_SHIFT) | MajorFrame;
	Packet = XHwIcap_Type1Write(XHI_FAR_MIN) | 1;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = MinorFrame;

	/*
	 * Setup CMD register - write configuration
	 */
	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
	Data = XHI_CMD_WCFG;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;

	/*
	 * Setup Packet header.
	 */
	TotalWords = InstancePtr->WordsPerFrame << 1;
	/*
	 * Create Type 2 Packet.
	 */
	Packet = XHwIcap_Type2Write(XHI_FDRI);

	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = 0;
	WriteBuffer[Index++] = TotalWords;

	/*
	 * Write the Header data into the FIFO and intiate the transfer of
	 * data present in the FIFO to the ICAP device
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, (u16 *)&WriteBuffer[0],
					Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	/*
	 * Write the modified frame data.
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr,
				(u16 *) &FrameData[InstancePtr->WordsPerFrame],
				InstancePtr->WordsPerFrame);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Write out the pad frame. The pad frame was read from the device
	 * before the data frame.
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, (u16 *) &FrameData[0],
				    InstancePtr->WordsPerFrame);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}


	/* Disable CRC */
	Index = 0;
	WriteBuffer[Index++] = XHI_DISABLED_AUTO_CRC_ONE;
	WriteBuffer[Index++] = XHI_DISABLED_AUTO_CRC_TWO;

	/*
	 * Setup CMD register - write configuration
	 */
	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
	Data = XHI_CMD_LFRM;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Intiate the transfer of data present in the FIFO to
	 * the ICAP device
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, &WriteBuffer[0], Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	/*
	 * Send DESYNC command
	 */
	Status = XHwIcap_CommandDesync(InstancePtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	return XST_SUCCESS;

}
Esempio n. 7
0
static ssize_t 
xhwicap_write(struct file *filp, const char *buf, size_t count, loff_t *f_pos)
{
        struct xhwicap_instance *inst;
	size_t write_count=count;
	XStatus status;
	const char *user_buf=buf;

	DBPRINTK("write\n");
	DBPRINTK("count is %lX\n",count);

	/* FIXME! Assume instance is first in list - this is bogus */
        inst = inst_list;
	if(!inst)
		return -ENODEV;

	/* Deal with any left overs from last time */
	DBPRINTK("PREAMBLE: %i bytes pending\n",inst->pendingByteCount);

	ASSERT(inst->pendingByteCount<4);

	/* Only enter the preamble if there is stuff left from last time */
	while(inst->pendingByteCount && inst->pendingByteCount<4 
		&& write_count)
	{
		unsigned char tmp;
		/* Accumulate into the pendingWord */
		copy_from_user(&tmp, user_buf++, 1);
		inst->pendingWord=(inst->pendingWord) << 8 | (tmp & 0xFF);
		inst->pendingByteCount++;
		write_count--;
	}

	/* Did we accumulated a full word? */
	if(inst->pendingByteCount==4)
	{
		DBPRINTK("Writing pendingword\n");
		/* Write the word to the buffer */
		XHwIcap_StorageBufferWrite(&(inst->HwIcap),0,inst->pendingWord);
		XHwIcap_DeviceWrite(&(inst->HwIcap), 0, 1);
		inst->pendingByteCount=0;
		inst->pendingWord=0;
	}

	ASSERT(write_count==0 || inst->pendingByteCount==0);

	/* Minimum possible chunk size is 4 bytes */
	while(write_count>3)
	{
		int chunk_word_count=0;
		size_t chunk_size, chunk_left;

		/* don't use full limit of BUFFER_BYTES, seems to
		   break the hardware.. 
		   Round down to nearest multiple of 4 */
		chunk_size=chunk_left=min(write_count, 
					(size_t)XHI_MAX_BUFFER_BYTES-8) & ~0x3;

		DBPRINTK("chunk size %lX\n",chunk_size);
		DBPRINTK("copying chunk to buffer\n");

		while(chunk_left)
		{
			u32 tmp;
			copy_from_user(&tmp, user_buf, 4);
			XHwIcap_StorageBufferWrite(&(inst->HwIcap),
							chunk_word_count++,
							tmp);
			user_buf+=4;
			chunk_left-=4;
		}

		ASSERT(chunk_word_count);

		DBPRINTK("done\nWriting chunk to device..");

		/* initiate write of private buffer to device */
		DBPRINTK("chunk_word_count:%X\n",chunk_word_count);

		status = XHwIcap_DeviceWrite(&(inst->HwIcap), 
						0, chunk_word_count);

		if(status==XST_BUFFER_TOO_SMALL)
			return -ENOSPC;
		else if(status==XST_DEVICE_BUSY)
			return -EBUSY;
		else if(status==XST_INVALID_PARAM)
			return -EINVAL;

		write_count-=chunk_word_count*4;
	}


	DBPRINTK("POSTAMBLE: %i bytes remaining\n",write_count);

	ASSERT(write_count<4);  /* No more than 3 bytes remaining */
	/*ASSERT(inst->pendingByteCount==0);   *//* pending buffer is empty */

	/* Put remaining bytes into the pending buffer */
	while(write_count)
	{
		unsigned char tmp;
		copy_from_user(&tmp, user_buf++, 1);
		inst->pendingWord=(inst->pendingWord) << 8 | (tmp & 0xFF);
		write_count--;
		inst->pendingByteCount++;
	}

	DBPRINTK("finished\n");
	return count-write_count;
}
Esempio n. 8
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/**
*
* This function does a minimal test on the HwIcap device and driver as a
* design example. The purpose of this function is to illustrate how to use
* the XHwIcap component using the interrupt mode.
*
* This function sends data and expects to receive the same data.
*
*
* @param	IntcInstancePtr is a pointer to the instance of the INTC component.
* @param	HwIcapInstancePtr is a pointer to the instance of HwIcap component.
* @param	HwIcapDeviceId is the Device ID of the HwIcap Device and is the
*		XPAR_<HWICAP_instance>_DEVICE_ID value from xparameters.h.
* @param	HwIcapIntrId is the interrupt Id and is typically
*		XPAR_<INTC_instance>_<HWICAP_instance>_IP2INTC_IRPT_INTR
*		value from xparameters.h .
*
* @return	XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note
*
* This function contains an infinite loop such that if interrupts are not
* working it may never return.
*
******************************************************************************/
int HwIcapIntrExample(XIntc *IntcInstancePtr, XHwIcap *HwIcapInstancePtr,
			u16 HwIcapDeviceId, u16 HwIcapIntrId)
{
	int Status;
	u32 Count;
	u8 Test;
	XHwIcap_Config *ConfigPtr;

	/*
	 * Initialize the HwIcap driver.
	 */
	ConfigPtr = XHwIcap_LookupConfig(HwIcapDeviceId);
	if (ConfigPtr == NULL) {
		return XST_FAILURE;
	}
	Status = XHwIcap_CfgInitialize(HwIcapInstancePtr,
					ConfigPtr,
					ConfigPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Perform a self-test to ensure that the hardware was built correctly.
	 */
	Status = XHwIcap_SelfTest(HwIcapInstancePtr);

	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Connect the HwIcap device to the interrupt subsystem such that
	 * interrupts can occur. This function is application specific.
	 */
	Status = HwIcapSetupInterruptSystem(IntcInstancePtr,
					HwIcapInstancePtr,
					HwIcapIntrId);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Setup the handler for the HwIcap that will be called from the
	 * interrupt context when an HwIcap status occurs, specify a pointer
	 * to the HwIcap driver instance as the callback reference so the
	 * handler is able to access the instance data.
	 */
	XHwIcap_SetInterruptHandler(HwIcapInstancePtr, HwIcapInstancePtr,
			 (XHwIcap_StatusHandler)HwIcapIntrHandler);

	/*
	 * Initialize the write buffer with pattern to write.
	 */
	for (Count = 0; Count < TEST_WRITE_BUFFER_SIZE;) {

		WriteBuffer[Count++] = XHI_DUMMY_PACKET;
		WriteBuffer[Count++] = XHI_SYNC_PACKET;
		WriteBuffer[Count++] = XHwIcap_Type1Read(XHI_IDCODE) | 1;
		WriteBuffer[Count++] = XHI_NOOP_PACKET;
		WriteBuffer[Count++] = XHI_NOOP_PACKET;
		WriteBuffer[Count++] = XHI_DUMMY_PACKET;
		WriteBuffer[Count++] = XHI_SYNC_PACKET;
		WriteBuffer[Count++] = XHwIcap_Type1Read(XHI_COR) | 1;
		WriteBuffer[Count++] = XHI_NOOP_PACKET;
		WriteBuffer[Count++] = XHI_NOOP_PACKET;
	}

	/*
	 * Enable the Write FIFO Half Full Interrupt.
	 */
	XHwIcap_IntrEnable(HwIcapInstancePtr, XHI_IPIXR_WRP_MASK);

	/*
	 * Write the the data to the device.
	 */
	TransferInProgress = TRUE;
	Status = XHwIcap_DeviceWrite(HwIcapInstancePtr,
					(u32 *) &WriteBuffer[0],
					TEST_WRITE_BUFFER_SIZE);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	/*
	 * Wait for the data to be written to the device.
	 */
	while (TransferInProgress);

	return XST_SUCCESS;
}
/**
*
* Reads one frame from the device and puts it in memory specified by the user.
*
* @param	InstancePtr - a pointer to the XHwIcap instance to be worked on.
* @param	Top - top (0) or bottom (1) half of device
* @param	Block - Block Address (XHI_FAR_CLB_BLOCK,
*		XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
* @param	HClkRow - selects the HClk Row
* @param	MajorFrame - selects the column
* @param	MinorFrame - selects frame inside column
* @param	FrameBuffer is a pointer to the memory where the frame read
*		from the device is stored
*
* @return	XST_SUCCESS else XST_FAILURE.
*
* @note		This is a blocking call.
*
*****************************************************************************/
int XHwIcap_DeviceReadFrame(XHwIcap *InstancePtr, long Top, long Block,
				long HClkRow, long MajorFrame, long MinorFrame,
				u32 *FrameBuffer)
{

	u32 Packet;
	u32 Data;
	u32 TotalWords;
	int Status;
	u32 WriteBuffer[READ_FRAME_SIZE];
	u32 Index = 0;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid(FrameBuffer != NULL);

	/*
	 * DUMMY and SYNC
	 */
	WriteBuffer[Index++] = XHI_DUMMY_PACKET;
	WriteBuffer[Index++] = XHI_SYNC_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Reset CRC
	 */
	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = XHI_CMD_RCRC;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Setup CMD register to read configuration
	 */
	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = XHI_CMD_RCFG;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Setup FAR register.
	 */
	Packet = XHwIcap_Type1Write(XHI_FAR) | 1;
	Data = XHwIcap_SetupFarV5(Top, Block, HClkRow,  MajorFrame, MinorFrame);
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = Data;

	/*
	 * Setup read data packet header.
	 * The frame will be preceeded by a dummy frame, and we need to read one
	 * extra word for V4 and V5 devices.
	 */
	TotalWords = (InstancePtr->WordsPerFrame << 1);
	/*
	 * Create Type one packet
	 */
	Packet = XHwIcap_Type1Read(XHI_FDRO) | TotalWords;
	WriteBuffer[Index++] = Packet;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;
	WriteBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Write the data to the FIFO and initiate the transfer of data
	 * present in the FIFO to the ICAP device
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, (u32 *)&WriteBuffer[0],
			Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	/*
	 * Wait till the write is done.
	 */
	while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE);


	/*
	 * Read the frame of the data including the NULL frame.
	 */
	Status = XHwIcap_DeviceRead(InstancePtr, FrameBuffer, TotalWords);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	/*
	 * Send DESYNC command
	 */
	Status = XHwIcap_CommandDesync(InstancePtr);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	return XST_SUCCESS;
};
/**
*
* Reads one frame from the device and puts it in the storage buffer.
*
* @param    InstancePtr - a pointer to the XHwIcap instance to be worked on.
*
* @param    Block - Block Address (XHI_FAR_CLB_BLOCK,
*           XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
*
* @param    MajorFrame - selects the column
*
* @param    MinorFrame - selects frame inside column
*
* @return   XST_SUCCESS, XST_BUFFER_TOO_SMALL or XST_INVALID_PARAM.
*
* @note     None.
*
*****************************************************************************/
XStatus XHwIcap_DeviceReadFrame(XHwIcap *InstancePtr, s32 Block, 
                                s32 MajorFrame, s32 MinorFrame) 
{

     s32 Packet;
     s32 Data;
     s32 TotalWords;
     XStatus Status;

    /* Make sure we aren't trying to read more than what we have room
     * for. */
    if (InstancePtr->BytesPerFrame > 
            (XHI_MAX_BUFFER_BYTES-XHI_HEADER_BUFFER_BYTES)) 
    {
        return XST_BUFFER_TOO_SMALL;
    }

    /* DUMMY and SYNC */
    XHwIcap_StorageBufferWrite(InstancePtr, 0, XHI_DUMMY_PACKET);
    XHwIcap_StorageBufferWrite(InstancePtr, 1, XHI_SYNC_PACKET);

    /* Setup CMD register to read configuration */
    Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
    Data = XHI_CMD_RCFG;
    XHwIcap_StorageBufferWrite(InstancePtr, 2,Packet);
    XHwIcap_StorageBufferWrite(InstancePtr, 3,Data);

    /* Setup FAR register. */
    Packet = XHwIcap_Type1Write(XHI_FAR) | 1;
    Data = XHwIcap_SetupFar(Block, MajorFrame, MinorFrame);
    XHwIcap_StorageBufferWrite(InstancePtr, 4,Packet);
    XHwIcap_StorageBufferWrite(InstancePtr, 5,Data);

    /* Setup read data packet header. */
    TotalWords = InstancePtr->WordsPerFrame << 1; /* mult by 2 */

    /* Create Type one packet */
    Packet = XHwIcap_Type1Read(XHI_FDRO) | TotalWords;
    XHwIcap_StorageBufferWrite(InstancePtr, 6,Packet);
    XHwIcap_StorageBufferWrite(InstancePtr, 7,0);  /* flush */
    XHwIcap_StorageBufferWrite(InstancePtr, 8,0);  /* flush */

    /* Write To ICAP. */
    Status = XHwIcap_DeviceWrite(InstancePtr, 0, 9);  
    if (Status != XST_SUCCESS) 
    {
        return Status;
    }

    /* Read pad frame (skip header). */
    Status = XHwIcap_DeviceRead(InstancePtr, XHI_HEADER_BUFFER_WORDS, 
                                InstancePtr->WordsPerFrame);
    if (Status != XST_SUCCESS) 
    {
        return Status;
    }

    /* Read data on top of pad frame (skip header). */
    Status = XHwIcap_DeviceRead(InstancePtr, XHI_HEADER_BUFFER_WORDS,
           InstancePtr->WordsPerFrame);
    if (Status != XST_SUCCESS) 
    {
        return Status;
    }

    /* send DESYNC command */
    Status = XHwIcap_CommandDesync(InstancePtr); 
    if (Status != XST_SUCCESS) 
    {
        return Status;
    }

   return XST_SUCCESS;
}; 
Esempio n. 11
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/**
*
* Reads one frame from the device and puts it in the storage buffer.
*
* @param    InstancePtr - a pointer to the XHwIcap instance to be worked on.
* @param    Top - top (0) or bottom (1) half of device
* @param    Block - Block Address (XHI_FAR_CLB_BLOCK,
*           XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
* @param    HClkRow - selects the HClk Row
* @param    MajorFrame - selects the column
* @param    MinorFrame - selects frame inside column
*
* @return   XST_SUCCESS, XST_BUFFER_TOO_SMALL or XST_INVALID_PARAM.
*
* @note     None.
*
*****************************************************************************/
XStatus XHwIcap_DeviceReadFrameV4(XHwIcap *InstancePtr, Xint32 Top,
                                Xint32 Block, Xint32 HClkRow,
                                Xint32 MajorFrame, Xint32 MinorFrame)
{

     Xint32 Packet;
     Xint32 Data;
     Xint32 TotalWords;
     XStatus Status;

    /* Make sure we aren't trying to read more than what we have room
     * for. */
    if (InstancePtr->BytesPerFrame >
            (XHI_MAX_BUFFER_BYTES-XHI_HEADER_BUFFER_BYTES))
    {
        return XST_BUFFER_TOO_SMALL;
    }

    /* DUMMY and SYNC */
    XHwIcap_StorageBufferWrite(InstancePtr, 0, XHI_DUMMY_PACKET);
    XHwIcap_StorageBufferWrite(InstancePtr, 1, XHI_SYNC_PACKET);
    XHwIcap_StorageBufferWrite(InstancePtr, 2, XHI_NOOP_PACKET);  /* flush */
    XHwIcap_StorageBufferWrite(InstancePtr, 3, XHI_NOOP_PACKET);  /* flush */

    /* Reset CRC */
    Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
    XHwIcap_StorageBufferWrite(InstancePtr, 4, Packet);
    XHwIcap_StorageBufferWrite(InstancePtr, 5, XHI_CMD_RCRC);
    XHwIcap_StorageBufferWrite(InstancePtr, 6, XHI_NOOP_PACKET);  /* flush */
    XHwIcap_StorageBufferWrite(InstancePtr, 7, XHI_NOOP_PACKET);  /* flush */

    /* Setup CMD register to read configuration */
    Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
    XHwIcap_StorageBufferWrite(InstancePtr, 8, Packet);
    XHwIcap_StorageBufferWrite(InstancePtr, 9, XHI_CMD_RCFG);
    XHwIcap_StorageBufferWrite(InstancePtr, 10, XHI_NOOP_PACKET);  /* flush */
    XHwIcap_StorageBufferWrite(InstancePtr, 11, XHI_NOOP_PACKET);  /* flush */
    XHwIcap_StorageBufferWrite(InstancePtr, 12, XHI_NOOP_PACKET);  /* flush */

    /* Setup FAR register. */
    Packet = XHwIcap_Type1Write(XHI_FAR) | 1;
    Data = XHwIcap_SetupFarV4(Top, Block, HClkRow,  MajorFrame, MinorFrame);
    XHwIcap_StorageBufferWrite(InstancePtr, 13, Packet);
    XHwIcap_StorageBufferWrite(InstancePtr, 14, Data);

    /* Setup read data packet header. */
    /* The frame will be preceeded by a dummy frame, and we need to read one
       extra word - see Configuration Guide Chapter 8 */
    TotalWords = (InstancePtr->WordsPerFrame << 1) + 1;

    /* Create Type one packet */
    Packet = XHwIcap_Type1Read(XHI_FDRO) | TotalWords;
    XHwIcap_StorageBufferWrite(InstancePtr, 15, Packet);
    XHwIcap_StorageBufferWrite(InstancePtr, 16, XHI_NOOP_PACKET);  /* flush */
    XHwIcap_StorageBufferWrite(InstancePtr, 17, XHI_NOOP_PACKET);  /* flush */

    /* Write To ICAP. */
    Status = XHwIcap_DeviceWrite(InstancePtr, 0, 18);
    if (Status != XST_SUCCESS)
    {
        return Status;
    }


    /* Read pad frame (skip header). */
/*
    Status = XHwIcap_DeviceRead(InstancePtr, XHI_HEADER_BUFFER_WORDS,
                                InstancePtr->WordsPerFrame);
    if (Status != XST_SUCCESS)
    {
        return Status;
    }

 */

    /* In previous versions we could read the pad frame and the real frame
       in two steps. However the behaviour of the opb_hwicap peripheral
       has changed, such that the first byte out of the ICAP port is
       always ignored. If we perform a read in two steps we will lose a
       byte in the middle - so we must read in one go.
    */

    /* Read data on top of pad frame (skip header). */
    Status = XHwIcap_DeviceRead(InstancePtr, XHI_HEADER_BUFFER_WORDS,
           TotalWords);
    if (Status != XST_SUCCESS)
    {
        return Status;
    }

    /* send DESYNC command */
    Status = XHwIcap_CommandDesync(InstancePtr);
    if (Status != XST_SUCCESS)
    {
        return Status;
    }

   return XST_SUCCESS;
};