int do_bootb_kintex7(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 FrameBuffer[8];
u32 BootAddress = simple_strtoul(argv[1], NULL, 16);
u32 Index = 0;
u32 Count;
if (argc < 2)
return -1;
if ((BootAddress < CONFIG_SYS_FLASH_BASE) || (BootAddress > (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)))
{
return -1;
}
/*
* Create the data to be written to the ICAP.
*/
FrameBuffer[Index++] = XHI_DUMMY_PACKET;
FrameBuffer[Index++] = XHI_SYNC_PACKET;
FrameBuffer[Index++] = XHI_NOOP_PACKET;
FrameBuffer[Index++] = 0x30020001; /* Type 1 write to WBSTAR */
FrameBuffer[Index++] = BootAddress;
FrameBuffer[Index++] = 0x30008001; /* Type 1 Write to CMD */
FrameBuffer[Index++] = XHI_CMD_IPROG;
FrameBuffer[Index++] = XHI_NOOP_PACKET;
/*
* Fill the FIFO with as many words as it will take (or as many as we have to send).
*/
while(Index > XHwIcap_GetWrFifoVacancy(HWICAP_BASEADDR));
for (Count = 0; Count < Index; Count++)
{
XHwIcap_FifoWrite(HWICAP_BASEADDR, FrameBuffer[Count]);
}
/*
* Start the transfer of the data from the FIFO to the ICAP device.
*/
XHwIcap_StartConfig(HWICAP_BASEADDR);
while ((XHwIcap_ReadReg(HWICAP_BASEADDR,XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
while (XHwIcap_IsDeviceBusy(HWICAP_BASEADDR) != 0);
while (XHwIcap_ReadReg(HWICAP_BASEADDR, XHI_CR_OFFSET) & XHI_CR_WRITE_MASK);
/* The code should never get here sice the FPGA should reset */
return -1;
}
/**
*
* This function returns the IDCODE of the target device.
*
* @param BaseAddress is the base address of the HwIcap instance.
* @param IdCode is the IDCODE of the part this code is running on.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE
*
* @note None
*
******************************************************************************/
u32 HwIcapLowLevelExample(u32 BaseAddress, u32 *IdCode)
{
u32 Index;
u32 Retries;
/*
* Write command sequence to the FIFO
*/
for (Index = 0; Index < HWICAP_EXAMPLE_BITSTREAM_LENGTH; Index++) {
XHwIcap_WriteReg(BaseAddress, XHI_WF_OFFSET, ReadId[Index]);
}
/*
* Start the transfer of the data from the FIFO to the ICAP device.
*/
XHwIcap_WriteReg(BaseAddress, XHI_CR_OFFSET, XHI_CR_WRITE_MASK);
/*
* Poll for done, which indicates end of transfer
*/
Retries = 0;
while ((XHwIcap_ReadReg(BaseAddress, XHI_SR_OFFSET) &
XHI_SR_DONE_MASK) != XHI_SR_DONE_MASK) {
Retries++;
if (Retries > XHI_MAX_RETRIES) {
/*
* Waited to long. Exit with error.
*/
printf("\r\nHwIcapLowLevelExample failed- retries \
failure. \r\n\r\n");
return XST_FAILURE;
}
}
/**
*
* This function returns the value of the specified configuration register.
*
* @param InstancePtr is a pointer to the XHwIcap instance.
* @param ConfigReg is a constant which represents the configuration
* register value to be returned. Constants specified in
* xhwicap_i.h.
* Examples: XHI_IDCODE, XHI_FLR.
* @param RegData is the value of the specified configuration
* register.
*
* @return XST_SUCCESS or XST_FAILURE
*
* @note This is a blocking call.
*
*****************************************************************************/
u32 XHwIcap_GetConfigReg(XHwIcap *InstancePtr, u32 ConfigReg, u32 *RegData)
{
int Status;
int EosRetries =0; /* Counter for checking EOS to become high */
#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
u16 FrameBuffer[READ_CFG_REG_COMMAND_SIZE];
u32 Retries =0;
#else
u32 FrameBuffer[READ_CFG_REG_COMMAND_SIZE];
#endif
u32 Index =0;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Create the data to be written to the ICAP.
*/
FrameBuffer[Index++] = XHI_DUMMY_PACKET;
#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
FrameBuffer[Index++] = XHI_SYNC_PACKET1;
FrameBuffer[Index++] = XHI_SYNC_PACKET2;
#else
FrameBuffer[Index++] = XHI_SYNC_PACKET;
#endif
FrameBuffer[Index++] = XHI_NOOP_PACKET;
FrameBuffer[Index++] = XHI_NOOP_PACKET;
#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
if (ConfigReg == XHI_IDCODE) {
FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x2;
}else {
FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x1;
}
#else
FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x1;
#endif
FrameBuffer[Index++] = XHI_NOOP_PACKET;
FrameBuffer[Index++] = XHI_NOOP_PACKET;
/*
* Check for EOS bit of Status Register. EOS bit becomes high after
* ICAP completes Start up sequence. Access to ICAP should start
* only after EOS bit becomes high.
*/
while((!(XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
XHI_SR_OFFSET)& XHI_SR_EOS_MASK))) {
if(EosRetries < XHI_MAX_RETRIES) {
EosRetries++;
}
else {
return XST_FAILURE;
}
}
/*
* Write the data to the FIFO and intiate the transfer of data present
* in the FIFO to the ICAP device.
*/
Status = XHwIcap_DeviceWrite(InstancePtr, &FrameBuffer[0], Index);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE);
while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
#if (XHI_FAMILY == XHI_DEV_FAMILY_V6) ||\
(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
/*
* Read the Config Register using DeviceRead since
* DeviceRead reads depending on ICAP Width for V6
* and 7 series devices
*/
XHwIcap_DeviceRead(InstancePtr, RegData, 1);
#else
XHwIcap_SetSizeReg(InstancePtr, 1);
if (ConfigReg == XHI_IDCODE) {
XHwIcap_SetSizeReg(InstancePtr, 2);
}
XHwIcap_StartReadBack(InstancePtr);
while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE) {
Retries++;
if (Retries > XHI_MAX_RETRIES) {
return XST_FAILURE;
}
}
while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
XHI_CR_OFFSET)) &
XHI_CR_READ_MASK);
/*
* Return the Register value
*/
*RegData = XHwIcap_FifoRead(InstancePtr);
if (ConfigReg == XHI_IDCODE) {
*RegData = ((*RegData << 16) |
(XHwIcap_FifoRead(InstancePtr)));
}
#endif
return XST_SUCCESS;
}
/**
*
* Run a self-test on the driver/device. The test
* - Writes to the Interrupt Enable Register and reads it back
* for comparison.
*
* @param InstancePtr is a pointer to the XHwIcap instance.
*
* @return
* - XST_SUCCESS if the value read from the register
* is the same as the value written.
* - XST_FAILURE otherwise
*
* @note None.
*
******************************************************************************/
int XHwIcap_SelfTest(XHwIcap *InstancePtr)
{
int Status = XST_SUCCESS;
u32 IeRegister;
u32 DgieRegister;
/*
* Assert the argument
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Save a copy of the Global Interrupt Enable Register and Interrupt
* Enable Register before writing them so that they can be restored.
*/
DgieRegister = XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
XHI_GIER_OFFSET);
IeRegister = XHwIcap_IntrGetEnabled(InstancePtr);
/*
* Disable the Global Interrupt
*/
XHwIcap_IntrGlobalDisable(InstancePtr);
/*
* Disable/Enable the interrupts and then verify that the register
* is read back correct.
*/
XHwIcap_IntrDisable(InstancePtr, XHI_IPIXR_ALL_MASK);
if (XHwIcap_IntrGetEnabled(InstancePtr) != 0x0) {
Status = XST_FAILURE;
}
XHwIcap_IntrEnable(InstancePtr, (XHI_IPIXR_WEMPTY_MASK |
XHI_IPIXR_RDP_MASK));
if (XHwIcap_IntrGetEnabled(InstancePtr) !=
(XHI_IPIXR_WEMPTY_MASK | XHI_IPIXR_RDP_MASK)) {
Status |= XST_FAILURE;
}
/*
* Restore the Interrupt Enable Register to the value before the
* test.
*/
XHwIcap_IntrDisable(InstancePtr, XHI_IPIXR_ALL_MASK);
if (IeRegister != 0) {
XHwIcap_IntrEnable(InstancePtr, IeRegister);
}
/*
* Restore the Global Interrupt Enable Register to the value
* before the test.
*/
XHwIcap_WriteReg(InstancePtr->HwIcapConfig.BaseAddress,
XHI_GIER_OFFSET, DgieRegister);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
