/** * * This function disables the interrupts for the GPIO * * @param IntcInstancePtr is a pointer to the Interrupt Controller * driver Instance * @param InstancePtr is a pointer to the GPIO driver Instance * @param IntrId is XPAR_<INTC_instance>_<GPIO_instance>_IP2INTC_IRPT_INTR * value from xparameters.h * @param IntrMask is the GPIO channel mask * * @return None * * @note None. * ******************************************************************************/ void GpioDisableIntr(XIntc* IntcInstancePtr, XGpio* InstancePtr, u16 IntrId, u16 IntrMask) { XGpio_InterruptDisable(InstancePtr, IntrMask); XIntc_Disable(IntcInstancePtr, IntrId); return; }
void sound_disable_int(void) { XIntc *intcp; intcp = &intc; XIntc_Disable(intcp, XPAR_XPS_INTC_0_PLB_AC97_0_INTERRUPT_INTR); }
/** * * This function disables the interrupts for the Timer. * * @param IntcInstancePtr is a reference to the Interrupt Controller * driver Instance. * @param IntrId is XPAR_<INTC_instance>_<Timer_instance>_VEC_ID * value from xparameters.h. * * @return None. * * @note None. * ******************************************************************************/ void TmrCtrDisableIntr(XIntc* IntcInstancePtr, u16 IntrId) { /* * Disable the interrupt for the timer counter */ XIntc_Disable(IntcInstancePtr, IntrId); return; }
//----------------------------------------------------------------------------------------------------// // @func - sys_disable_interrupt //! @desc //! Disable interrupts from the specified interrupt source //! @param //! - intr_id is the zero based ID of the interrupt //! @return //! - Nothing //! @note //! - None //----------------------------------------------------------------------------------------------------// void sys_disable_interrupt (int_id_t intr_id) { #ifdef MB_XILKERNEL // Disallow playing with timer interrupt if (intr_id == SYSTMR_INTR_ID ) return; #endif XIntc_Disable (&sys_intc, intr_id); }
/** * * This function disables the interrupts for the Timer. * * @param IntcInstancePtr is a reference to the Interrupt Controller * driver Instance. * @param IntrId is XPAR_<INTC_instance>_<Timer_instance>_VEC_ID * value from xparameters.h. * * @return None. * * @note None. * ******************************************************************************/ void TmrCtrDisableIntr(INTC* IntcInstancePtr, u16 IntrId) { /* * Disable the interrupt for the timer counter */ #ifdef XPAR_INTC_0_DEVICE_ID XIntc_Disable(IntcInstancePtr, IntrId); #else /* Disconnect the interrupt */ XScuGic_Disable(IntcInstancePtr, IntrId); XScuGic_Disconnect(IntcInstancePtr, IntrId); #endif return; }
void vPortDisableInterrupt( uint8_t ucInterruptID ) { int32_t lReturn; /* An API function is provided to disable an interrupt in the interrupt controller because the interrupt controller instance variable is private to this file. */ lReturn = prvEnsureInterruptControllerIsInitialised(); if( lReturn == pdPASS ) { XIntc_Disable( &xInterruptControllerInstance, ucInterruptID ); } configASSERT( lReturn ); }
static void TimerInterrupt(void *CallBackRef, u8 TmrCtrNumber) { timers[count] = TmrCtrNumber; times[count] = getTimerCaptureValue(TmrCtrNumber); count++; if (count == CAPTURES) { XIntc_Disable(&timerIntCtrl, XPAR_INTC_0_TMRCTR_0_VEC_ID); stopTimer(0); stopTimer(1); int x; for (x = 0; x < count; x++) xil_printf("\r\n%d %d", timers[x], times[x]); } }
/** * * Sets the normal interrupt mode for the specified interrupt in the Interrupt * Mode Register. In Cascade mode disconnects handler from corresponding Slave * controller IVAR register depending on the Id and sets all interrupt sources * of the Slave controller as normal interrupts. * * @param InstancePtr is a pointer to the XIntc instance to be worked on. * @param Id contains the ID of the interrupt source and should be in the * range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the * highest priority interrupt. * * @return None. * * @note * Slave controllers in Cascade Mode should have all as Fast * interrupts or Normal interrupts, mixed interrupts are not * supported * ****************************************************************************/ void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id) { u32 Imr; u32 CurrentIER; u32 Mask; XIntc_Config *CfgPtr; /* * Assert the arguments */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->CfgPtr->FastIntr == TRUE); if (Id > 31) { /* Enable user required Id in Slave controller */ CfgPtr = XIntc_LookupConfig(Id/32); /* Get the Enabled Interrupts */ CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET); /* Convert from integer id to bit mask */ Mask = XIntc_BitPosMask[(Id%32)]; /* Disable the Interrupt if it was enabled before calling * this function */ if (CurrentIER & Mask) { XIntc_Disable(InstancePtr, Id); } /* Slave controllers in Cascade Mode should have all as Fast * interrupts or Normal interrupts, mixed interrupts are not * supported */ XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0x0); if (CfgPtr->IntVectorAddr == 0x0) { XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET + (Id * 4), 0x10); } else { XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET + (Id * 4), CfgPtr->IntVectorAddr); } /* Enable the Interrupt if it was enabled before calling this * function */ if (CurrentIER & Mask) { XIntc_Enable(InstancePtr, Id); } } else { /* Get the Enabled Interrupts */ CurrentIER = XIntc_In32(InstancePtr->BaseAddress + XIN_IER_OFFSET); Mask = XIntc_BitPosMask[Id];/* Convert from integer id to bit mask */ /* Disable the Interrupt if it was enabled before * calling this function */ if (CurrentIER & Mask) { XIntc_Disable(InstancePtr, Id); } /* * Disable the selected interrupt as Fast Interrupt by reading the * interrupt mode register and then modifying only the * specified interrupt id */ Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET); XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET, Imr & ~Mask); if (InstancePtr->CfgPtr->IntVectorAddr == 0x0) { XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET + (Id * 4), 0x10); } else { XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET + (Id * 4), InstancePtr->CfgPtr->IntVectorAddr); } /* Enable the Interrupt if it was enabled before * calling this function */ if (CurrentIER & Mask) { XIntc_Enable(InstancePtr, Id); } } }
/** * * Makes the connection between the Id of the interrupt source and the * associated handler that is to run when the interrupt is recognized.In Cascade * mode, connects handler to corresponding Slave controller IVAR register * depending on the Id and sets all interrupt sources of the Slave controller as * fast interrupts. * * @param InstancePtr is a pointer to the XIntc instance to be worked on. * @param Id contains the ID of the interrupt source and should be in the * range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being * the highest priority interrupt. * @param Handler to the handler for that interrupt. * * @return * - XST_SUCCESS * * @note * Slave controllers in Cascade Mode should have all as Fast * interrupts or Normal interrupts, mixed interrupts are not * supported * * WARNING: The handler provided as an argument will overwrite any handler * that was previously connected. * ****************************************************************************/ int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id, XFastInterruptHandler Handler) { u32 Imr; u32 CurrentIER; u32 Mask; XIntc_Config *CfgPtr; /* * Assert the arguments */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); Xil_AssertNonvoid(Handler != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->CfgPtr->FastIntr == TRUE); if (Id > 31) { /* Enable user required Id in Slave controller */ CfgPtr = XIntc_LookupConfig(Id/32); if (CfgPtr->FastIntr != TRUE) { /*Fast interrupts of slave controller are not enabled*/ return XST_FAILURE; } /* Get the Enabled Interrupts */ CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET); /* Convert from integer id to bit mask */ Mask = XIntc_BitPosMask[(Id%32)]; /* Disable the Interrupt if it was enabled before calling * this function */ if (CurrentIER & Mask) { XIntc_Disable(InstancePtr, Id); } XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET + ((Id%32) * 4), (u32) Handler); /* Slave controllers in Cascade Mode should have all as Fast * interrupts or Normal interrupts, mixed interrupts are not * supported */ XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF); /* Enable the Interrupt if it was enabled before calling this * function */ if (CurrentIER & Mask) { XIntc_Enable(InstancePtr, Id); } } else { /* Get the Enabled Interrupts */ CurrentIER = XIntc_In32(InstancePtr->BaseAddress + XIN_IER_OFFSET); /* Convert from integer id to bit mask */ Mask = XIntc_BitPosMask[Id]; /* Disable the Interrupt if it was enabled before calling * this function */ if (CurrentIER & Mask) { XIntc_Disable(InstancePtr, Id); } XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET + (Id * 4), (u32) Handler); Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET); XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET, Imr | Mask); /* Enable the Interrupt if it was enabled before * calling this function */ if (CurrentIER & Mask) { XIntc_Enable(InstancePtr, Id); } } return XST_SUCCESS; }
void timer_disable() { XIntc_Disable(&intCtrl_Timer, TIMER_IR_ID); }
void disable_display_timer(void) { XIntc *intcp; intcp = &intc; XIntc_Disable(intcp, XPAR_XPS_INTC_0_XPS_TIMER_1_INTERRUPT_INTR); }
void disable_ps2_int() { XIntc *intcp; intcp = &intc; XIntc_Disable(intcp, XPAR_XPS_INTC_0_PS2CORE_0_PS2_INTERRUPT_INTR); }
/** * This function will mask a interrupt. * @param vector the interrupt number */ void rt_hw_interrupt_mask(int vector) { /* disable interrupt */ XIntc_Disable(&int_ctl,vector); }