/** * * This function setups the interrupt system for an Spi device. * This function is application specific since the actual system may or may not * have an interrupt controller. The Spi device could be directly connected to * a processor without an interrupt controller. The user should modify this * function to fit the application. * * @param IntcInstancePtr is a pointer to the instance of the Intc device. * @param SpiInstancePtr is a pointer to the instance of the Spi device. * @param SpiIntrId is the interrupt Id for an SPI device. * * @return XST_SUCCESS if successful, otherwise XST_FAILURE. * * @note None. * ******************************************************************************/ static int SpiSetupIntrSystem(XScuGic *IntcInstancePtr, XSpiPs *SpiInstancePtr, u16 SpiIntrId) { int Status; #ifndef TESTAPP_GEN XScuGic_Config *IntcConfig; /* Instance of the interrupt controller */ Xil_ExceptionInit(); /* * Initialize the interrupt controller driver so that it is ready to * use. */ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Connect the interrupt controller interrupt handler to the hardware * interrupt handling logic in the processor. */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, IntcInstancePtr); #endif /* * Connect the device driver handler that will be called when an * interrupt for the device occurs, the handler defined above performs * the specific interrupt processing for the device. */ Status = XScuGic_Connect(IntcInstancePtr, SpiIntrId, (Xil_ExceptionHandler)XSpiPs_InterruptHandler, (void *)SpiInstancePtr); if (Status != XST_SUCCESS) { return Status; } /* * Enable the interrupt for the Spi device. */ XScuGic_Enable(IntcInstancePtr, SpiIntrId); #ifndef TESTAPP_GEN /* * Enable interrupts in the Processor. */ Xil_ExceptionEnable(); #endif return XST_SUCCESS; }
XStatus InitInterruptController(INTC* intc) { int Status; // Start the interrupt controller #ifdef XPAR_INTC_0_DEVICE_ID // Initialize the driver instance RETURN_ON_FAILURE(XIntc_Initialize(intc, INTC_DEVICE_ID)); RETURN_ON_FAILURE(XIntc_Start(intc, XIN_REAL_MODE)); #else XScuGic_Config *GicConfig; GicConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); XScuGic_CfgInitialize(intc, GicConfig, GicConfig->CpuBaseAddress); Status = XScuGic_SelfTest(intc); if (Status != XST_SUCCESS) { return XST_FAILURE; } #endif Xil_ExceptionInit(); /* * register the interrupt controller handler with the exception table. * This is in fact the ISR dispatch routine, calling our ISRs */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler) INTC_HANDLER, intc); Xil_ExceptionEnable(); return XST_SUCCESS; }
static void prvSetupHardware( void ) { BaseType_t xStatus; XScuGic_Config *pxGICConfig; /* Ensure no interrupts execute while the scheduler is in an inconsistent state. Interrupts are automatically enabled when the scheduler is started. */ portDISABLE_INTERRUPTS(); /* Obtain the configuration of the GIC. */ pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID ); /* Sanity check the FreeRTOSConfig.h settings are correct for the hardware. */ configASSERT( pxGICConfig ); configASSERT( pxGICConfig->CpuBaseAddress == ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) ); configASSERT( pxGICConfig->DistBaseAddress == configINTERRUPT_CONTROLLER_BASE_ADDRESS ); /* Install a default handler for each GIC interrupt. */ xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress ); configASSERT( xStatus == XST_SUCCESS ); ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ /* Initialise the LED port. */ vParTestInitialise(); /* The Xilinx projects use a BSP that do not allow the start up code to be altered easily. Therefore the vector table used by FreeRTOS is defined in FreeRTOS_asm_vectors.S, which is part of this project. Switch to use the FreeRTOS vector table. */ vPortInstallFreeRTOSVectorTable(); }
int zynqMP_r5_gic_initialize() { u32 Status; Xil_ExceptionDisable(); XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */ /* * Initialize the interrupt controller driver */ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Register the interrupt handler to the hardware interrupt handling * logic in the ARM processor. */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler) zynqMP_r5_irq_isr, &InterruptController); Xil_ExceptionEnable(); return 0; }
int zynqMP_r5_gic_initialize() { #ifndef USE_FREERTOS u32 Status; XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */ /* * Initialize the interrupt controller driver */ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(&xInterruptController, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Register the interrupt handler to the hardware interrupt handling * logic in the ARM processor. */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler,&xInterruptController); Xil_ExceptionEnable(); #endif OpenAMPInstPtr.IntrID = VRING1_IPI_INTR_VECT; XScuGic_Connect(&xInterruptController, VRING1_IPI_INTR_VECT, (Xil_ExceptionHandler)zynqMP_r5_irq_isr, &OpenAMPInstPtr); return 0; }
int setup_interrupt() { //This functions sets up the interrupt on the ARM int result; XScuGic_Config *pCfg = XScuGic_LookupConfig(XPAR_SCUGIC_0_DEVICE_ID); if (pCfg == NULL){ print("Interrupt Configuration Lookup Failed\n\r"); return XST_FAILURE; } result = XScuGic_CfgInitialize(&ScuGic,pCfg,pCfg->CpuBaseAddress); if(result != XST_SUCCESS){ return result; } // self test result = XScuGic_SelfTest(&ScuGic); if(result != XST_SUCCESS){ return result; } // Initialize the exception handler Xil_ExceptionInit(); // Register the exception handler Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,&ScuGic); //Enable the exception handler Xil_ExceptionEnable(); // Connect the Voice Rec ISR to the exception table result = XScuGic_Connect(&ScuGic,XPAR_FABRIC_VOICEREC_0_INTERRUPT_INTR,(Xil_InterruptHandler)hls_voicerec_isr,&HlsVoiceRec); if(result != XST_SUCCESS){ return result; } // Enable the Voice Rec ISR XScuGic_Enable(&ScuGic,XPAR_FABRIC_VOICEREC_0_INTERRUPT_INTR); return XST_SUCCESS; }
/** * * This function runs a self-test on the driver/device. This is a destructive * test. This function is an example of how to use the interrupt controller * driver component (XScuGic) and the hardware device. This function is designed * to work without any hardware devices to cause interrupts. It may not return * if the interrupt controller is not properly connected to the processor in * either software or hardware. * * This function relies on the fact that the interrupt controller hardware * has come out of the reset state such that it will allow interrupts to be * simulated by the software. * * @param DeviceId is device ID of the Interrupt Controller Device, * typically XPAR_<INTC_instance>_DEVICE_ID value from * xparameters.h. * * @return XST_SUCCESS to indicate success, otherwise XST_FAILURE. * * @note None. * ******************************************************************************/ int ScuGicSelfTestExample(u16 DeviceId) { int Status; static XScuGic_Config *GicConfig; /* * Initialize the interrupt controller driver so that it is ready to * use. */ GicConfig = XScuGic_LookupConfig(DeviceId); if (NULL == GicConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(&IntcInstance, GicConfig, GicConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } return XST_SUCCESS; }
//////////////////////////// InitializeInterruptSystem//////////////////////////////// int InitializeInterruptSystem(u16 deviceID) { int Status; GicConfig = XScuGic_LookupConfig (deviceID); if(NULL == GicConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(&InterruptController, GicConfig, GicConfig->CpuBaseAddress); if(Status != XST_SUCCESS) { return XST_FAILURE; } Status = SetUpInterruptSystem(&InterruptController); if(Status != XST_SUCCESS) { return XST_FAILURE; } Status = XScuGic_Connect (&InterruptController, XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR, (Xil_ExceptionHandler) InterruptHandler, NULL); if(Status != XST_SUCCESS) { return XST_FAILURE; } XScuGic_Enable(&InterruptController, XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR ); return XST_SUCCESS; }
static void init_interrupt() { Xil_ExceptionInit(); if ((icconf = XScuGic_LookupConfig(XPAR_PS7_SCUGIC_0_DEVICE_ID)) == NULL) return; if (XScuGic_CfgInitialize(&ic, icconf, icconf->CpuBaseAddress) != XST_SUCCESS) return; Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler) XScuGic_InterruptHandler, &ic); if (XScuGic_Connect(&ic, PL_INT_ID, interrupt_handler, NULL) != XST_SUCCESS) return; XScuGic_SetPriorityTriggerType(&ic, PL_INT_ID, 0, /*highest priority*/ 3); /* 3 - rising edge, 1 - active high */ XScuGic_Enable(&ic, PL_INT_ID); Xil_ExceptionEnable(); }
int IntcInitFunction(u16 DeviceId, XGpio *GpioInstancePtr) { XScuGic_Config *IntcConfig; int status; // Interrupt controller initialisation IntcConfig = XScuGic_LookupConfig(DeviceId); status = XScuGic_CfgInitialize(&INTCInst, IntcConfig, IntcConfig->CpuBaseAddress); if(status != XST_SUCCESS) return XST_FAILURE; // Call to interrupt setup status = InterruptSystemSetup(&INTCInst); if(status != XST_SUCCESS) return XST_FAILURE; // Connect GPIO interrupt to handler status = XScuGic_Connect(&INTCInst, INTC_GPIO_INTERRUPT_ID, (Xil_ExceptionHandler)RF_INTr_Handler, (void *)GpioInstancePtr); if(status != XST_SUCCESS) return XST_FAILURE; // Enable GPIO interrupts interrupt XGpio_InterruptEnable(GpioInstancePtr, 1); XGpio_InterruptGlobalEnable(GpioInstancePtr); // Enable GPIO and timer interrupts in the controller XScuGic_Enable(&INTCInst, INTC_GPIO_INTERRUPT_ID); return XST_SUCCESS; }
static int SetupInterruptSystem(XScuGic *GicInstancePtr, XScuTimer *TimerInstancePtr, u16 TimerIntrId) { XScuGic_Config *IntcConfig; //GIC config Xil_ExceptionInit(); //initialise the GIC IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); XScuGic_CfgInitialize(GicInstancePtr, IntcConfig, IntcConfig->CpuBaseAddress); //connect to the hardware Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, GicInstancePtr); //set up the timer interrupt XScuGic_Connect(GicInstancePtr, TimerIntrId, (Xil_ExceptionHandler)TimerIntrHandler, (void *)TimerInstancePtr); //enable the interrupt for the Timer at GIC XScuGic_Enable(GicInstancePtr, TimerIntrId); //enable interrupt on the timer XScuTimer_EnableInterrupt(TimerInstancePtr); // Enable interrupts in the Processor. Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); return XST_SUCCESS; }
static int SetupIntrSystem(XScuGic * IntcInstancePtr, XAxiDma * AxiDmaPtr, u16 TxIntrId) { int Status; XScuGic_Config *IntcConfig; /* * Initialize the interrupt controller driver so that it is ready to * use. */ IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3); /* * Connect the device driver handler that will be called when an * interrupt for the device occurs, the handler defined above performs * the specific interrupt processing for the device. */ Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,(Xil_InterruptHandler)TxIntrHandler,AxiDmaPtr); if (Status != XST_SUCCESS) { return Status; } XScuGic_Enable(IntcInstancePtr, TxIntrId); /* Enable interrupts from the hardware */ Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,(void *)IntcInstancePtr); Xil_ExceptionEnable(); return XST_SUCCESS; }
/** * * This function sets up the interrupt system so interrupts can occur for the * Uart. This function is application-specific. The user should modify this * function to fit the application. * * @param IntcInstancePtr is a pointer to the instance of the INTC. * @param UartInstancePtr contains a pointer to the instance of the UART * driver which is going to be connected to the interrupt * controller. * @param UartIntrId is the interrupt Id and is typically * XPAR_<UARTPS_instance>_INTR value from xparameters.h. * * @return XST_SUCCESS if successful, otherwise XST_FAILURE. * * @note None. * ****************************************************************************/ static int SetupInterruptSystem(XScuGic *IntcInstancePtr, XUartPs *UartInstancePtr, u16 UartIntrId) { int Status; #ifndef TESTAPP_GEN XScuGic_Config *IntcConfig; /* Config for interrupt controller */ /* * Initialize the interrupt controller driver */ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Connect the interrupt controller interrupt handler to the * hardware interrupt handling logic in the processor. */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler) XScuGic_InterruptHandler, IntcInstancePtr); #endif /* * Connect a device driver handler that will be called when an * interrupt for the device occurs, the device driver handler * performs the specific interrupt processing for the device */ Status = XScuGic_Connect(IntcInstancePtr, UartIntrId, (Xil_ExceptionHandler) XUartPs_InterruptHandler, (void *) UartInstancePtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Enable the interrupt for the device */ XScuGic_Enable(IntcInstancePtr, UartIntrId); #ifndef TESTAPP_GEN /* * Enable interrupts */ Xil_ExceptionEnable(); #endif return XST_SUCCESS; }
int ScuGicExample(u16 DeviceId) { int Status; /* * Initialize the interrupt controller driver so that it is ready to * use. */ GicConfig = XScuGic_LookupConfig(DeviceId); if (NULL == GicConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(&InterruptController, GicConfig, GicConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Perform a self-test to ensure that the hardware was built * correctly */ Status = XScuGic_SelfTest(&InterruptController); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Setup the Interrupt System */ Status = SetUpInterruptSystem(&InterruptController); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Connect a device driver handler that will be called when an * interrupt for the device occurs, the device driver handler performs * the specific interrupt processing for the device */ Status = XScuGic_Connect(&InterruptController, INTC_DEVICE_INT_ID, (Xil_ExceptionHandler)DeviceDriverHandler, (void *)&InterruptController); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Enable the interrupt for the device and then cause (simulate) an * interrupt so the handlers will be called */ XScuGic_Enable(&InterruptController, INTC_DEVICE_INT_ID); return XST_SUCCESS; }
/** * This function setups the interrupt system so interrupts can occur for the * IIC device. The function is application-specific since the actual system may * or may not have an interrupt controller. The IIC device could be directly * connected to a processor without an interrupt controller. The user should * modify this function to fit the application. * * @param IicInstPtr contains a pointer to the instance of the IIC device * which is going to be connected to the interrupt controller. * * @return XST_SUCCESS if successful else XST_FAILURE. * * @note None. * ******************************************************************************/ static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr) { int Status; XIIC *I2cInstancePtr; INTC *IntcPtr; I2cInstancePtr = &I2cLibPtr->I2cInstance; IntcPtr = &I2cLibPtr->IntcInstance; XScuGic_Config *IntcConfig; /* * Initialize the interrupt controller driver so that it is ready to * use. */ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } XScuGic_SetPriorityTriggerType(IntcPtr, IIC_INTR_ID, 0xA0, 0x3); /* * Connect the interrupt handler that will be called when an * interrupt occurs for the device. */ Status = XScuGic_Connect(IntcPtr, IIC_INTR_ID, (Xil_InterruptHandler) XIicPs_MasterInterruptHandler, I2cInstancePtr); if (Status != XST_SUCCESS) { return Status; } /* * Enable the interrupt for the IIC device. */ XScuGic_Enable(IntcPtr, IIC_INTR_ID); /* * Initialize the exception table and register the interrupt * controller handler with the exception table */ Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler) INTC_HANDLER, IntcPtr); /* Enable non-critical exceptions */Xil_ExceptionEnable(); return XST_SUCCESS; }
/** * * This function setups the interrupt system such that interrupts can occur * for the IIC. This function is application specific since the actual * system may or may not have an interrupt controller. The IIC could be * directly connected to a processor without an interrupt controller. The * user should modify this function to fit the application. * * @param IicPsPtr contains a pointer to the instance of the Iic * which is going to be connected to the interrupt controller. * * @return XST_SUCCESS if successful, otherwise XST_FAILURE. * * @note None. * *******************************************************************************/ static int SetupInterruptSystem(XIicPs *IicPsPtr) { int Status; XScuGic_Config *IntcConfig; /* Instance of the interrupt controller */ Xil_ExceptionInit(); /* * Initialize the interrupt controller driver so that it is ready to * use. */ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Connect the interrupt controller interrupt handler to the hardware * interrupt handling logic in the processor. */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &InterruptController); /* * Connect the device driver handler that will be called when an * interrupt for the device occurs, the handler defined above performs * the specific interrupt processing for the device. */ Status = XScuGic_Connect(&InterruptController, IIC_INT_VEC_ID, (Xil_InterruptHandler)XIicPs_MasterInterruptHandler, (void *)IicPsPtr); if (Status != XST_SUCCESS) { return Status; } /* * Enable the interrupt for the Iic device. */ XScuGic_Enable(&InterruptController, IIC_INT_VEC_ID); /* * Enable interrupts in the Processor. */ Xil_ExceptionEnable(); return XST_SUCCESS; }
int IntcInitFunction(u16 DeviceId, XTmrCtr *TmrInstancePtr, XGpio *GpioInstancePtr, XDmaPs *DmaPtr) { XScuGic_Config *IntcConfig; int status; // Interrupt controller initialization IntcConfig = XScuGic_LookupConfig(DeviceId); status = XScuGic_CfgInitialize(&INTCInst, IntcConfig, IntcConfig->CpuBaseAddress); if(status != XST_SUCCESS) return XST_FAILURE; // Call to interrupt setup status = InterruptSystemSetup(&INTCInst); if(status != XST_SUCCESS) return XST_FAILURE; // Connect GPIO interrupt to handler status = XScuGic_Connect(&INTCInst, INTC_GPIO_INTERRUPT_ID, (Xil_ExceptionHandler)BTN_Intr_Handler, (void *)GpioInstancePtr); if(status != XST_SUCCESS) return XST_FAILURE; // Connect timer interrupt to handler status = XScuGic_Connect(&INTCInst, INTC_TMR_INTERRUPT_ID, (Xil_ExceptionHandler)TMR_Intr_Handler, (void *)TmrInstancePtr); if(status != XST_SUCCESS) return XST_FAILURE; // Enable GPIO interrupts interrupt XGpio_InterruptEnable(GpioInstancePtr, 1); XGpio_InterruptGlobalEnable(GpioInstancePtr); // Enable GPIO interrupts in the controller XScuGic_Enable(&INTCInst, INTC_GPIO_INTERRUPT_ID); // Enable timer interrupts in the controller XScuGic_Enable(&INTCInst, INTC_TMR_INTERRUPT_ID); //Lab7 addition starts here // Connect DMA interrupt to handler XScuGic_Connect(&INTCInst,DMA_FAULT_INTR,(Xil_InterruptHandler)XDmaPs_FaultISR,(void *)DmaPtr); XScuGic_Connect(&INTCInst,DMA_DONE_INTR_0,(Xil_InterruptHandler)XDmaPs_DoneISR_0,(void *)DmaPtr); // Enable DMA interrupts in the controller XScuGic_Enable(&INTCInst, DMA_DONE_INTR_0); //Lab7 addition ends here return XST_SUCCESS; }
/* * The application must provide a function that configures a peripheral to * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() * in FreeRTOSConfig.h to call the function. This file contains a function * that is suitable for use on the Zynq SoC. */ void vConfigureTickInterrupt( void ) { static XScuGic xInterruptController; /* Interrupt controller instance */ BaseType_t xStatus; extern void FreeRTOS_Tick_Handler( void ); XScuTimer_Config *pxTimerConfig; XScuGic_Config *pxGICConfig; const uint8_t ucRisingEdge = 3; /* This function is called with the IRQ interrupt disabled, and the IRQ interrupt should be left disabled. It is enabled automatically when the scheduler is started. */ /* Ensure XScuGic_CfgInitialize() has been called. In this demo it has already been called from prvSetupHardware() in main(). */ pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID ); xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress ); configASSERT( xStatus == XST_SUCCESS ); ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ /* The priority must be the lowest possible. */ XScuGic_SetPriorityTriggerType( &xInterruptController, XPAR_SCUTIMER_INTR, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucRisingEdge ); /* Install the FreeRTOS tick handler. */ xStatus = XScuGic_Connect( &xInterruptController, XPAR_SCUTIMER_INTR, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, ( void * ) &xTimer ); configASSERT( xStatus == XST_SUCCESS ); ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ /* Initialise the timer. */ pxTimerConfig = XScuTimer_LookupConfig( XPAR_SCUTIMER_DEVICE_ID ); xStatus = XScuTimer_CfgInitialize( &xTimer, pxTimerConfig, pxTimerConfig->BaseAddr ); configASSERT( xStatus == XST_SUCCESS ); ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ /* Enable Auto reload mode. */ XScuTimer_EnableAutoReload( &xTimer ); /* Ensure there is no prescale. */ XScuTimer_SetPrescaler( &xTimer, 0 ); /* Load the timer counter register. */ XScuTimer_LoadTimer( &xTimer, XSCUTIMER_CLOCK_HZ / configTICK_RATE_HZ ); /* Start the timer counter and then wait for it to timeout a number of times. */ XScuTimer_Start( &xTimer ); /* Enable the interrupt for the xTimer in the interrupt controller. */ XScuGic_Enable( &xInterruptController, XPAR_SCUTIMER_INTR ); /* Enable the interrupt in the xTimer itself. */ vClearTickInterrupt(); XScuTimer_EnableInterrupt( &xTimer ); }
/* * The application must provide a function that configures a peripheral to * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() * in FreeRTOSConfig.h to call the function. This file contains a function * that is suitable for use on the Zynq SoC. */ void vConfigureTickInterrupt( void ) { XTtcPs_Config *pxTimerConfig; BaseType_t xStatus; XScuGic_Config *pxGICConfig; static XScuGic xInterruptController; /* Interrupt controller instance */ uint16_t usInterval; uint8_t ucPrescale = 0; const uint8_t ucRisingEdge = 3; /* This function is called with the IRQ interrupt disabled, and the IRQ interrupt should be left disabled. It is enabled automatically when the scheduler is started. */ /* Ensure XScuGic_CfgInitialize() has been called. In this demo it has already been called from prvSetupHardware() in main(). */ pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID ); xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress ); configASSERT( xStatus == XST_SUCCESS ); ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ /* The interrupt priority must be the lowest possible. */ XScuGic_SetPriorityTriggerType( &xInterruptController, tickINTERRUPT_ID, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucRisingEdge ); /* Install the FreeRTOS tick handler. */ xStatus = XScuGic_Connect( &xInterruptController, tickINTERRUPT_ID, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, NULL ); configASSERT( xStatus == XST_SUCCESS ); ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ /* Initialise the Triple Timer Counter (TTC) that is going to be used to generate the tick interrupt. */ pxTimerConfig = XTtcPs_LookupConfig( tickTTC_ID ); xStatus = XTtcPs_CfgInitialize( &xTimerInstance, pxTimerConfig, pxTimerConfig->BaseAddress ); configASSERT( xStatus == XST_SUCCESS ); ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ /* Configure the interval to be the require tick rate. */ XTtcPs_CalcIntervalFromFreq( &xTimerInstance, configTICK_RATE_HZ, &usInterval, &ucPrescale ); XTtcPs_SetInterval( &xTimerInstance, usInterval ); XTtcPs_SetPrescaler( &xTimerInstance, ucPrescale ); /* Interval mode used. */ XTtcPs_SetOptions( &xTimerInstance, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE ); /* Start the timer. */ XTtcPs_Start( &xTimerInstance ); /* Enable the interrupt in the interrupt controller. */ XScuGic_Enable( &xInterruptController, tickINTERRUPT_ID ); /* Enable the interrupt in the timer itself. */ XTtcPs_EnableInterrupts( &xTimerInstance, XTTCPS_IXR_INTERVAL_MASK ); }
/****************************************************************************** * @brief Initialize Interrupt Controller * * @param None. * * @return None. ******************************************************************************/ void Ps7IntcInit(void) { XScuGic_Config *IntcConfig; /* Initialize the interrupt controller driver */ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); XScuGic_CfgInitialize(&IntcInstance, IntcConfig, IntcConfig->CpuBaseAddress); Xil_ExceptionInit(); /* Connect the interrupt controller interrupt handler to the hardware interrupt logic */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &IntcInstance); }
/** * * This function setups the interrupt system such that interrupts can occur for * the USB controller. This function is application specific since the actual * system may or may not have an interrupt controller. The USB controller could * be directly connected to a processor without an interrupt controller. The * user should modify this function to fit the application. * * @param IntcInstancePtr is a pointer to instance of the Intc controller. * @param UsbInstancePtr is a pointer to instance of the USB controller. * @param UsbIntrId is the Interrupt Id and is typically * XPAR_<INTC_instance>_<USB_instance>_VEC_ID value * from xparameters.h * * @return * - XST_SUCCESS if successful * - XST_FAILURE on error * ******************************************************************************/ static int UsbSetupIntrSystem(XScuGic *IntcInstancePtr, XUsbPs *UsbInstancePtr, u16 UsbIntrId) { int Status; XScuGic_Config *IntcConfig; /* * Initialize the interrupt controller driver so that it is ready to * use. */ IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } Xil_ExceptionInit(); /* * Connect the interrupt controller interrupt handler to the hardware * interrupt handling logic in the processor. */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, IntcInstancePtr); /* * Connect the device driver handler that will be called when an * interrupt for the device occurs, the handler defined above performs * the specific interrupt processing for the device. */ Status = XScuGic_Connect(IntcInstancePtr, UsbIntrId, (Xil_ExceptionHandler)XUsbPs_IntrHandler, (void *)UsbInstancePtr); if (Status != XST_SUCCESS) { return Status; } /* * Enable the interrupt for the device. */ XScuGic_Enable(IntcInstancePtr, UsbIntrId); /* * Enable interrupts in the Processor. */ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); return XST_SUCCESS; }
/** * This function sets up the interrupt system for the example. The processing * contained in this function assumes the hardware system was built with * and interrupt controller. * * @param None. * * @return A status indicating XST_SUCCESS or a value that is contained in * xstatus.h. * * @note None. * *****************************************************************************/ int zed_ali3_controller_demo_SetupInterruptSystem(zed_ali3_controller_demo_t *pDemo) { int Result; /* * Initialize the interrupt controller driver so that it is ready to * use. */ pDemo->pIntcConfig = XScuGic_LookupConfig(pDemo->uDeviceId_IRQ_Touch); if (NULL == pDemo->pIntcConfig) { return XST_FAILURE; } Result = XScuGic_CfgInitialize(&(pDemo->Intc), pDemo->pIntcConfig, pDemo->pIntcConfig->CpuBaseAddress); if (Result != XST_SUCCESS) { return XST_FAILURE; } XScuGic_SetPriorityTriggerType(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch, 0xA0, 0x3); /* * Connect the interrupt handler that will be called when an * interrupt occurs for the device. */ Result = XScuGic_Connect(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch, (Xil_ExceptionHandler)TouchIsr, pDemo); if (Result != XST_SUCCESS) { return Result; } /* * Enable the PS interrupts for the touch controller hardware device. */ XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch); /* * Initialize the exception table and register the interrupt * controller handler with the exception table */ Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &(pDemo->Intc)); /* Enable non-critical exceptions */ Xil_ExceptionEnable(); return XST_SUCCESS; }
static void SetupInterruptSystem(XScuGic *GicInstancePtr, u32 *FPGAPtr, u16 FPGAIntrId, XGpioPs *Gpio, u16 GpioIntrId) { XScuGic_Config *IntcConfig; //GIC config Xil_ExceptionInit(); //initialise the GIC IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); XScuGic_CfgInitialize(GicInstancePtr, IntcConfig, IntcConfig->CpuBaseAddress); //connect to the hardware Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, GicInstancePtr); //set up the timer interrupt XScuGic_Connect(GicInstancePtr, FPGAIntrId, (Xil_ExceptionHandler)FPGAIntrHandler, (void *)FPGAPtr); //set up the GPIO interrupt XScuGic_Connect(GicInstancePtr, GpioIntrId, (Xil_ExceptionHandler)XGpioPs_IntrHandler, (void *)Gpio); //Enable interrupts for all the pins in bank 0. XGpioPs_SetIntrTypePin(Gpio, pbsw, XGPIOPS_IRQ_TYPE_EDGE_RISING); //Set the handler for gpio interrupts. XGpioPs_SetCallbackHandler(Gpio, (void *)Gpio, GPIOIntrHandler); //Enable the GPIO interrupts of Bank 0. XGpioPs_IntrEnablePin(Gpio, pbsw); //Enable the interrupt for the GPIO device. XScuGic_Enable(GicInstancePtr, GpioIntrId); //enable the interrupt for the Timer at GIC XScuGic_Enable(GicInstancePtr, FPGAIntrId); // Enable interrupts in the Processor. Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); printf("Interrupt Set Up\n\r"); }
/** * * This function is used by the TestAppGen generated application to setup * the interrupt controller. * * @param IntcInstancePtr is the reference to the Interrupt Controller * instance. * @param DeviceId is device ID of the Interrupt Controller Device, * typically XPAR_<INTC_instance>_DEVICE_ID value from * xparameters.h. * * @return XST_SUCCESS to indicate success, otherwise XST_FAILURE. * * @note None. * ******************************************************************************/ int ScuGicInterruptSetup(XScuGic *IntcInstancePtr, u16 DeviceId) { int Status; static XScuGic_Config *GicConfig; /* * Initialize the interrupt controller driver so that it is ready to * use. */ GicConfig = XScuGic_LookupConfig(DeviceId); if (NULL == GicConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(IntcInstancePtr, GicConfig, GicConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Initialize the exception table. */ Xil_ExceptionInit(); /* * Connect the interrupt controller interrupt handler to the hardware * interrupt handling logic in the processor. */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, IntcInstancePtr); /* * Enable exceptions. */ Xil_ExceptionEnable(); return XST_SUCCESS; }
int initialize_gic() { int status; XScuGic_Config* gic_config; /* * Initialize the interrupt controller driver so that it is ready to * use. */ gic_config = XScuGic_LookupConfig(INTC_DEVICE_ID); if (gic_config == NULL) return XST_FAILURE; status = XScuGic_CfgInitialize(&m_gic, gic_config, gic_config->CpuBaseAddress); if (status != XST_SUCCESS) return XST_FAILURE; return XST_SUCCESS; }
EN_RESULT SetupInterruptSystem() { XScuGic_Config* pInterruptControllerConfig; // Initialize the exception table. Xil_ExceptionInit(); // Initialize the interrupt controller driver so that it's ready to use. pInterruptControllerConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == pInterruptControllerConfig) { return EN_ERROR_NULL_POINTER; } RETURN_IF_XILINX_CALL_FAILED(XScuGic_CfgInitialize(&g_interruptController, pInterruptControllerConfig, pInterruptControllerConfig->CpuBaseAddress), EN_ERROR_FAILED_TO_INITIALISE_INTERRUPT_CONTROLLER); // Register the interrupt controller handler with the exception table. Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &g_interruptController); // Connect the device driver handler that will be called when an I2C interrupt // occurs RETURN_IF_XILINX_CALL_FAILED(XScuGic_Connect(&g_interruptController, IIC_INTR_ID, (Xil_InterruptHandler)XIicPs_MasterInterruptHandler, &g_XIicPsInstance), EN_ERROR_FAILED_TO_INITIALISE_INTERRUPT_CONTROLLER); // Enable the interrupts for the IIC device. XScuGic_Enable(&g_interruptController, IIC_INTR_ID); // INSERT ANY FURTHER INTERRUPT ENABLES HERE // // Enable non-critical exceptions. Xil_ExceptionEnable(); return EN_SUCCESS; }
XStatus fnInitInterruptController(intc *psIntc) { int result = 0; #ifdef XPAR_XINTC_NUM_INSTANCES // Init driver instance RETURN_ON_FAILURE(XIntc_Initialize(psIntc, INTC_DEVICE_ID)); // Start interrupt controller RETURN_ON_FAILURE(XIntc_Start(psIntc, XIN_REAL_MODE)); Xil_ExceptionInit(); // Register the interrupt controller handler with the exception table. // This is in fact the ISR dispatch routine, which calls our ISRs Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XIntc_InterruptHandler, psIntc); #endif #ifdef XPAR_SCUGIC_0_DEVICE_ID XScuGic_Config *IntcConfig; /* * Initialize the interrupt controller driver so that it is ready to * use. */ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } result = XScuGic_CfgInitialize(psIntc, IntcConfig, IntcConfig->CpuBaseAddress); if (result != XST_SUCCESS) { return XST_FAILURE; } #endif //Xil_ExceptionEnable(); return XST_SUCCESS; }
static void prvSetupInterruptController (void) { int Status; XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */ /* * Initialize the interrupt controller driver */ IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID); if (IntcConfig == NULL) { return; } Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return; } }
static int SetupIntrSystem(INTC *IntcInstancePtr) { int Status; XScuGic_Config *IntcConfig; IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == IntcConfig) { return XST_FAILURE; } Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)INTC_HANDLER, IntcInstancePtr); Xil_ExceptionEnable(); return XST_SUCCESS; }
/** * @brief init_irq() - Initialize GIC and connect IPI interrupt * This function will initialize the GIC and connect the IPI * interrupt. * * @return 0 - succeeded, non-0 for failures */ int init_irq() { int ret = 0; XScuGic_Config *IntcConfig; /* The configuration parameters of * the interrupt controller */ Xil_ExceptionDisable(); /* * Initialize the interrupt controller driver */ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (NULL == IntcConfig) { return (int)XST_FAILURE; } ret = XScuGic_CfgInitialize(&xInterruptController, IntcConfig, IntcConfig->CpuBaseAddress); if (ret != XST_SUCCESS) { return (int)XST_FAILURE; } /* * Register the interrupt handler to the hardware interrupt handling * logic in the ARM processor. */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &xInterruptController); Xil_ExceptionEnable(); /* Connect IPI Interrupt ID with libmetal ISR */ XScuGic_Connect(&xInterruptController, IPI_IRQ_VECT_ID, (Xil_ExceptionHandler)metal_xlnx_irq_isr, (void *)IPI_IRQ_VECT_ID); XScuGic_Enable(&xInterruptController, IPI_IRQ_VECT_ID); return 0; }