int main(int argc, char **argv) {
t_arch* arch = (t_arch *)my_calloc(1,sizeof(t_arch));
t_type_descriptor *types;
int numTypes;
;
if (argc - 1 != 3) {
printf(
"Error: Unexpected # of arguments. Expected 3 found %d arguments\n",
argc);
print_help();
}
printf(
"------------------------------------------------------------------------------\n");
printf(
"- Read architecture file and print library data structures into an output file\n");
printf(
"------------------------------------------------------------------------------\n\n");
printf("Inputs: \n"
"architecture %s \n"
"timing_driven %d \n"
"output file %s\n", argv[1], atoi(argv[2]), argv[3]);
printf("Reading in architecture\n");
/* function declarations */
XmlReadArch(argv[1], (boolean) atoi(argv[2]), arch, &types, &numTypes);
printf("Printing Results\n");
EchoArch(argv[3], types, numTypes, arch);
printf("Done\n");
free(arch);
return 0;
}
/*---------------------------------------------------------------------------------------------
* (function: startOdin)
*-------------------------------------------------------------------------------------------*/
void OdinInterface::startOdin()
{
int num_types;
init_options();
//global_args.verilog_file = "/home/kons/Documents/OdinSVN/odin-ii-read-only/ODIN_II/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_mod.v";
/* read the FPGA architecture file */
if (global_args.arch_file != NULL)
{
fprintf(stderr, "Reading FPGA Architecture file\n");
XmlReadArch(global_args.arch_file, (boolean)FALSE, &Arch, &type_descriptors, &num_types);
}
if (!global_args.blif_file)
{
/* High level synthesis tool */
do_high_level_synthesis();
}
else
{
read_blif(global_args.blif_file);
}
}
int main(int argc, char **argv)
{
int num_types;
printf("--------------------------------------------------------------------\n");
printf("Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)\n");
printf("Email: [email protected] and [email protected] for support issues\n\n");
/* get the command line options */
get_options(argc, argv);
/* read the confirguration file .. get options presets the config values just in case theyr'e not read in with config file */
if (global_args.config_file != NULL)
{
printf("Reading Configuration file\n");
read_config_file(global_args.config_file);
}
/* read the FPGA architecture file */
if (global_args.arch_file != NULL)
{
printf("Reading FPGA Architecture file\n");
#ifdef VPR5
t_clocks ClockDetails = { 0 };
t_power PowerDetails = { 0 };
XmlReadArch(global_args.arch_file, (boolean)FALSE, &Arch, &type_descriptors, &num_types, &ClockDetails, &PowerDetails);
#endif
#ifdef VPR6
XmlReadArch(global_args.arch_file, (boolean)FALSE, &Arch, &type_descriptors, &num_types);
#endif
}
#ifdef VPR5
if (global_args.activation_blif_file != NULL && global_args.activation_netlist_file != NULL)
{
do_activation_estimation(num_types, type_descriptors);
}
else
#endif
{
if (!global_args.blif_file)
{
/* High level synthesis tool */
do_high_level_synthesis();
}
else
{
read_blif(global_args.blif_file);
}
/* Simulate netlist */
do_simulation_of_netlist();
}
#ifdef VPR6
report_mult_distribution();
report_add_distribution();
report_sub_distribution();
deregister_hard_blocks();
#endif
return 0;
}
