void FA_NAKED( init_hw ) ( void ) { // Initialize ports (ATmega32U4) DDRE = DDE ; PORTE = PEPU ; DDRF = DDF ; PORTF = PFPU ; // #endif // Initialize timers SetTMPS( 0, 64 ) ; // Set T0 prescaler to / 64 for query & us delay SetTMPS( 1, 1024 ) ; // Set T1 prescaler to / 1024 for ms delay EICRA = _B1(ISC01) | _B1(ISC00) ; // Need INT0 on rising edges Delay_1024( T0DEL200MS ) ; // Allow the stick to boot for ( ;; ) // Forever.. { Flash_LED_12MS() ; // Flash LED and wait Delay_1024( T0DEL200MS ) ; // Try to read a data packet, QueryFFP( 0, 126 ) ; // don't know how long - let it time out Flash_LED_12MS() ; // Analyze clock count if ( ! ~sw_clkcnt ) sw_clkcnt = 0 ; if ( sw_clkcnt == (16 + 1) // FFP/PP in 3-bit mode || sw_clkcnt == (48 + 1) ) // 3DPP in 1-bit mode { if ( InitFFPro() ) // found FFP/PP { break ; // break forever } } dis3DP_INT() ; } dis3DP_INT() ; // Disable INT cli() ; // Disable interrupts sw_buttons = BUTMSK ; // All buttons released RET() ; // naked also means no ret.. }
static void FA_NORETURN( reboot ) ( void ) { cli() ; // Disable interrupts USBCON = _B0(USBE) | _B1(FRZCLK) ; // Kill USB for ( ;; ) // Wait for watchdog to bite (.5s) ; }
// returns the battery voltage in 10mV units // for instance: get_battery_voltage() returning 278 equals a voltage of 2.78V uint16_t get_battery_voltage(void) { power_adc_enable(); ADMUX = _B0(REFS1) | _B1(REFS0) // AVCC with external capacitor at AREF pin #ifndef PREC_BATT_VOLTAGE | _BV(ADLAR) // left adjust ADC - drops the two LSBs #endif | 0b11110; // measure 1.1v internal reference ADCSRA = _BV(ADEN) // enable ADC | _BV(ADPS2) | _BV(ADPS1) | _BV(ADPS0) // prescaler 128 | _BV(ADSC); // start conversion // wait for the conversion to finish loop_until_bit_is_set(ADCSRA, ADIF); // remember the result #ifdef PREC_BATT_VOLTAGE uint16_t adc_result = ADC; #else uint8_t adc_result = ADCH; #endif // clear the ADIF bit by writing one SetBit(ADCSRA, ADIF); ADCSRA = 0; // disable ADC power_adc_disable(); // ADC power off #ifdef PREC_BATT_VOLTAGE return 112640 / adc_result; #else return 28050 / adc_result; #endif }
int fw_l1p_init( void ) { TRACE_ENTRY(TRACE_L1P); uint64_t cfg_spec = L1P_CFG_SPEC_l1_hit_fwd_l2; uint64_t cfg_pf_usr = L1P_CFG_PF_USR_dfetch_depth(2) | L1P_CFG_PF_USR_dfetch_max_footprint(7) | L1P_CFG_PF_USR_ifetch_depth(0) | L1P_CFG_PF_USR_ifetch_max_footprint(2) | L1P_CFG_PF_USR_pf_stream_est_on_dcbt // [DISABLED] | L1P_CFG_PF_USR_pf_stream_optimistic | L1P_CFG_PF_USR_pf_stream_prefetch_enable | L1P_CFG_PF_USR_pf_stream_establish_enable | L1P_CFG_PF_USR_pf_adaptive_enable | L1P_CFG_PF_USR_pf_adaptive_throttle(0xF) ; /* UNUSED | L1P_CFG_PF_USR_pf_list_enable */ uint64_t cfg_pf_sys = L1P_CFG_PF_SYS_msync_timer(7+3) | L1P_CFG_PF_SYS_pfhint_enable | L1P_CFG_PF_SYS_whint_evict_enable | L1P_CFG_PF_SYS_whint_cracked_enable | L1P_CFG_PF_SYS_lock_prefetch | L1P_CFG_PF_SYS_dcbfl_discard | L1P_CFG_PF_SYS_pf_adaptive_total_depth(24) | L1P_CFG_PF_SYS_pf_hit_enable | L1P_CFG_PF_SYS_pf_stream_l2_op_immediate ; if(!FW_DD1_WORKAROUNDS_ENABLED()) { cfg_pf_sys |= L1P_CFG_PF_SYS_wrap_bug_dd2_bhv; } uint64_t cfg_wc = L1P_CFG_WC_wc_enable | L1P_CFG_WC_wc_suppress_if_all_be | L1P_CFG_WC_wc_aging ; uint64_t cfg_to = L1P_CFG_TO_to_en | L1P_CFG_TO_to_reload_en | L1P_CFG_TO_to_duration(0x3) ; uint64_t cfg_upc = L1P_CFG_UPC_ENABLE | L1P_CFG_UPC_STREAM; out64_sync((void *)L1P_CFG_SPEC,cfg_spec); out64_sync((void *)L1P_CFG_PF_USR,cfg_pf_usr); out64_sync((void *)L1P_CFG_PF_SYS,L1P_CFG_PF_SYS_pf_adaptive_reset|cfg_pf_sys); out64_sync((void *)L1P_CFG_PF_SYS,cfg_pf_sys); out64_sync((void *)L1P_CFG_WC,cfg_wc); out64_sync((void *)L1P_CFG_TO,cfg_to); out64_sync((void *)L1P_CFG_UPC,cfg_upc); /* Enable L1p hardware error interrupts */ uint64_t esr_gea = // [disabled] L1P_ESR_int_list_0 | // [disabled] L1P_ESR_int_list_1 | // [disabled] L1P_ESR_int_list_2 | // [disabled] L1P_ESR_int_list_3 | // [disabled] L1P_ESR_int_list_4 | // [disabled] L1P_ESR_int_speculation_0 | // [disabled] L1P_ESR_int_speculation_1 | // [disabled] L1P_ESR_int_speculation_2 | // [disabled] L1P_ESR_int_speculation_3 | // [disabled] L1P_ESR_err_valid_timeout | [see bqcbugs #1612] L1P_ESR_err_luq_ovfl | L1P_ESR_err_sr_p | L1P_ESR_err_sr_rd_valid_p | L1P_ESR_err_sw_p | L1P_ESR_err_si_ecc_ue | L1P_ESR_err_si_p | L1P_ESR_err_sda_p_ue | L1P_ESR_err_rqra_p | L1P_ESR_err_reload_ecc_ue_x2 | L1P_ESR_err_rira_p | L1P_ESR_err_gctr_p | L1P_ESR_err_lu_state_p | L1P_ESR_err_lu_ttype | // [5470] L1P_ESR_err_lu_dcr_abort | L1P_ESR_err_mmio_async | L1P_ESR_err_mmio_state_p | L1P_ESR_err_mmio_timeout | L1P_ESR_err_mmio_priv | L1P_ESR_err_mmio_rdata_p | L1P_ESR_err_mmio_wdata_p | L1P_ESR_err_mmio_dcrs_timeout | L1P_ESR_err_mmio_dcrs_priv | L1P_ESR_err_mmio_dcrs_par | L1P_ESR_err_dcrm_crit | L1P_ESR_err_dcrm_noncrit | // [5470] L1P_ESR_err_dcrm_mc | L1P_ESR_err_tag_timeout | L1P_ESR_err_hold_timeout | L1P_ESR_err_ditc_req_x2 | L1P_ESR_err_pfd_addr_p | L1P_ESR_err_pfd_avalid_p | L1P_ESR_err_pfd_fill_pnd_p | L1P_ESR_err_pfd_hit_pnd_p | L1P_ESR_err_pfd_stream_p | L1P_ESR_err_pfd_depth_p | L1P_ESR_err_pfd_clone_p | L1P_ESR_err_hitq_p | L1P_ESR_err_sd_p | L1P_ESR_err_pf2dfc_p | L1P_ESR_err_wccm_p_x2 | L1P_ESR_err_wccm_wcd_p_x2 | L1P_ESR_err_lu_wcd_p | L1P_ESR_err_lu_current_p | L1P_ESR_err_l2cmd | L1P_ESR_err_lu_dcr_dbus_p | L1P_ESR_err_luq_p | L1P_ESR_err_sda_phase_p | L1P_ESR_slice_sel_ctrl_perr | L1P_ESR_redun_ctrl_perr ; // +------------------------------------------------------------------------------------------+ // | NOTE: For production environments, we mask L1P correctables during the early part of the | // | boot. The TakeCPU hook is what allows us to unmask. | // +------------------------------------------------------------------------------------------+ if ( ! PERS_ENABLED(PERS_ENABLE_TakeCPU) ) { esr_gea |= L1P_ESR_err_si_ecc | L1P_ESR_err_reload_ecc_x2 | L1P_ESR_err_sda_p ; } out64_sync( (void *)L1P_ESR_GEA, esr_gea ); #ifndef FW_PREINSTALLED_GEA_HANDLERS uint64_t mask[3] = { L1P_GEA_MASK_0, L1P_GEA_MASK_1, L1P_GEA_MASK2 }; fw_installGeaHandler( fw_l1p_machineCheckHandler, mask ); #endif unsigned core = ProcessorCoreID(); DCRWritePriv( L1P_DCR(core,INTERRUPT_STATE_A_CONTROL_HIGH), L1P_DCR__INTERRUPT_STATE_A_CONTROL_HIGH__LOCAL_RING_set(1) | // Global Interrupt 0 ); DCRWritePriv( L1P_DCR(core,INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH), // [5470] L1P_DCR__INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH__BAD_ADDRESS_set(1) | // [5470] L1P_DCR__INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH__BAD_PRIV_set(1) | L1P_DCR__INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH__BAD_DATA_PARITY_set(1) | L1P_DCR__INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH__BAD_ADDRESS_PARITY_set(1) | 0 ); if(A2_isDD1()) { *(volatile uint64_t*)L1P_CFG_CLK_GATE = _B1(61,1); } else { *(volatile uint64_t*)L1P_CFG_CLK_GATE = L1P_CFG_CLK_GATE_clk_on_sw_req; } if(!FW_DD1_WORKAROUNDS_ENABLED()) { *(volatile uint64_t*)L1P_CFG_CHICKEN |= L1P_CFG_CHICKEN_DD2; } fw_l1p_resetCEThresholds(); #if 0 if ( ProcessorCoreID() == 2 ) { // DO NOT INTEGRATE THIS CODE!!!!!!!!!!! uint64_t inject = L1P_ESR_err_reload_ecc_x2 | //L1P_ESR_err_si_ecc | //L1P_ESR_err_reload_ecc_ue_x2 | 0 ; out64_sync((void *)L1P_ESR_INJ_DCR(ProcessorCoreID()), inject ); ppc_msync(); out64_sync((void *)L1P_ESR_INJ_DCR(ProcessorCoreID()), 0 ); ppc_msync(); } #endif TRACE_EXIT(TRACE_L1P); return( 0 ); }