static void prvConfigureEtherCAndEDMAC( void )
{
/* Initialisation code taken from Renesas example project. */
/* TODO: Check bit 5 */
ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
/* Set the EDMAC interrupt priority. */
_IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
/* TODO: Check bit 5 */
/* Enable interrupts of interest only. */
EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
/* EDMAC */
EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
#ifdef __LIT
EDMAC.EDMR.BIT.DE = 1;
#endif
EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
/* Enable the interrupt... */
_IEN( _ETHER_EINT ) = 1;
}
void vSetupHighFrequencyTimer( void )
{
/* Timer CMT2 is used to generate the interrupts, and CMT3 is used
to measure the jitter. */
/* Enable compare match timer 2 and 3. */
MSTP( CMT2 ) = 0;
MSTP( CMT3 ) = 0;
/* Interrupt on compare match. */
CMT2.CMCR.BIT.CMIE = 1;
/* Set the compare match value. */
CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) -1 ) / 8 );
/* Divide the PCLK by 8. */
CMT2.CMCR.BIT.CKS = 0;
CMT3.CMCR.BIT.CKS = 0;
/* Enable the interrupt... */
_IEN( _CMT2_CMI2 ) = 1;
/* ...and set its priority to the maximum possible, this is above the priority
set by configMAX_SYSCALL_INTERRUPT_PRIORITY so will nest. */
_IPR( _CMT2_CMI2 ) = timerHIGHEST_PRIORITY;
/* Start the timers. */
CMT.CMSTR1.BIT.STR2 = 1;
CMT.CMSTR1.BIT.STR3 = 1;
}
BaseType_t xPortStartScheduler( void )
{
extern void vApplicationSetupTimerInterrupt( void );
/* Use pxCurrentTCB just so it does not get optimised away. */
if( pxCurrentTCB != NULL )
{
/* Call an application function to set up the timer that will generate the
tick interrupt. This way the application can decide which peripheral to
use. A demo application is provided to show a suitable example. */
vApplicationSetupTimerInterrupt();
/* Enable the software interrupt. */
_IEN( _ICU_SWINT ) = 1;
/* Ensure the software interrupt is clear. */
_IR( _ICU_SWINT ) = 0;
/* Ensure the software interrupt is set to the kernel priority. */
_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the first task. */
prvStartFirstTask();
}
/* Just to make sure the function is not optimised away. */
( void ) vSoftwareInterruptISR();
/* Should not get here. */
return pdFAIL;
}
/* The RX port uses this callback function to configure its tick interrupt.
This allows the application to choose the tick interrupt source.
***NOTE***: configTICK_VECTOR must be set in FreeRTOSConfig.h to be correct for
whichever vector is used. */
void vApplicationSetupTimerInterrupt( void )
{
const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL;
/* Disable register write protection. */
SYSTEM.PRCR.WORD = ulEnableRegisterWrite;
/* Enable compare match timer 0. */
MSTP( CMT0 ) = 0;
/* Interrupt on compare match. */
CMT0.CMCR.BIT.CMIE = 1;
/* Set the compare match value. */
CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );
/* Divide the PCLK by 8. */
CMT0.CMCR.BIT.CKS = 0;
/* Enable the interrupt... */
_IEN( _CMT0_CMI0 ) = 1;
/* ...and set its priority to the application defined kernel priority. */
_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the timer. */
CMT.CMSTR0.BIT.STR0 = 1;
/* Reneable register protection. */
SYSTEM.PRCR.WORD = ulDisableRegisterWrite;
}
/******************************************************************************
Function Name : vApplicationSetupTimerInterrupt
Description : setup tick timer
Arguments : none
Return value : none
******************************************************************************/
void vApplicationSetupTimerInterrupt( void )
{
/* protect off */
SYSTEM.PRCR.WORD = 0xA502;
/* Enable compare match timer 0. */
MSTP( CMT0 ) = 0;
/* Interrupt on compare match. */
//CMT0.CMCR.BIT.CMIE = 1;
/* Divide the PCLK by 8. */
//CMT0.CMCR.BIT.CKS = 0;
CMT0.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @48MHz
/* Set the compare match value. */
CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1);
/* Enable the interrupt... */
_IEN( _CMT0_CMI0 ) = 1;
/* ...and set its priority to the application defined kernel priority. */
_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the timer. */
CMT.CMSTR0.BIT.STR0 = 1;
/* protect on */
SYSTEM.PRCR.WORD = 0xA500;
}
void vApplicationSetupTimerInterrupt(void)
{
//Disable protection
SYSTEM.PRCR.WORD = 0xA50B;
//Cancel CMT0 module stop state
MSTP(CMT0) = 0;
//Enable protection
SYSTEM.PRCR.WORD = 0xA500;
//Select PCLK/8 clock
CMT0.CMCR.BIT.CKS = 0;
//Set the compare match value
CMT0.CMCOR = ((PCLK_HZ / configTICK_RATE_HZ) - 1) / 8;
//Interrupt on compare match
CMT0.CMCR.BIT.CMIE = 1;
//Set interrupt priority
_IPR(_CMT0_CMI0) = configKERNEL_INTERRUPT_PRIORITY;
//Enable compare match interrupt
_IEN(_CMT0_CMI0) = 1;
//Start timer
CMT.CMSTR0.BIT.STR0 = 1;
}
void R_SWITCHES_Init (void)
{
/* Unlock protection register */
MPC.PWPR.BYTE &= 0x7F;
/* Unlock MPC registers */
MPC.PWPR.BYTE |= 0x40;
/* Make switch pins inputs. */
PORT3.PDR.BYTE &= 0xFC;
PORTE.PDR.BYTE &= 0xEF;
/* Set port mode registers for switches. */
PORT3.PMR.BYTE &= 0xFC;
PORTE.PMR.BYTE &= 0xEF;
MPC_P30PFS_REG = 0x40; /* P30 is used as IRQ pin */
MPC_P31PFS_REG = 0x40; /* P31 is used as IRQ pin */
MPC_PE4PFS_REG = 0x40; /* PE4 is used as IRQ pin */
/* Set IRQ type (falling edge) */
ICU.IRQCR[ SW1_IRQ_NUMBER ].BYTE = 0x04;
ICU.IRQCR[ SW2_IRQ_NUMBER ].BYTE = 0x04;
ICU.IRQCR[ SW3_IRQ_NUMBER ].BYTE = 0x04;
/* Set interrupt priorities, which must be below
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
_IPR( X_IRQ(SW1_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
_IPR( X_IRQ(SW2_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
_IPR( X_IRQ(SW3_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
/* Clear any pending interrupts */
_IR( X_IRQ(SW1_IRQ_NUMBER) ) = 0;
_IR( X_IRQ(SW2_IRQ_NUMBER) ) = 0;
_IR( X_IRQ(SW3_IRQ_NUMBER) ) = 0;
/* Enable the interrupts */
_IEN( X_IRQ(SW1_IRQ_NUMBER) ) = 1;
_IEN( X_IRQ(SW2_IRQ_NUMBER) ) = 1;
_IEN( X_IRQ(SW3_IRQ_NUMBER) ) = 1;
}
static void prvSetupTimerInterrupt( void )
{
/* Unlock. */
SYSTEM.PRCR.WORD = portUNLOCK_KEY;
/* Enable CMT0. */
MSTP( CMT0 ) = 0;
/* Lock again. */
SYSTEM.PRCR.WORD = portLOCK_KEY;
/* Interrupt on compare match. */
CMT0.CMCR.BIT.CMIE = 1;
/* Set the compare match value. */
CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
/* Divide the PCLK. */
#if portCLOCK_DIVISOR == 512
{
CMT0.CMCR.BIT.CKS = 3;
}
#elif portCLOCK_DIVISOR == 128
{
CMT0.CMCR.BIT.CKS = 2;
}
#elif portCLOCK_DIVISOR == 32
{
CMT0.CMCR.BIT.CKS = 1;
}
#elif portCLOCK_DIVISOR == 8
{
CMT0.CMCR.BIT.CKS = 0;
}
#else
{
#error Invalid portCLOCK_DIVISOR setting
}
#endif
/* Enable the interrupt... */
_IEN( _CMT0_CMI0 ) = 1;
/* ...and set its priority to the application defined kernel priority. */
_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the timer. */
CMT.CMSTR0.BIT.STR0 = 1;
}
/**
* switch to the first thread,it just call one time
*
* @author LXZ (2014/11/8)
*
* @param rt_uint32_t to
*/
void rt_hw_context_switch_to(rt_uint32_t to)
{
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = to;
rt_thread_switch_interrupt_flag = 1;
/* enable interrupt*/
_IEN( _ICU_SWINT ) = 1;
/*clear the interrupt flag*/
_IR( _ICU_SWINT ) = 0;
_IPR( _ICU_SWINT ) = MAX_SYSCALL_INTERRUPT_PRIORITY + 1;
/*touch the software interrupt*/
ENTER_INTERRUPT();
/*wait for first thread start up*/
while(1);
}
BaseType_t xPortStartScheduler( void )
{
/* Use pxCurrentTCB just so it does not get optimised away. */
if( pxCurrentTCB != NULL )
{
/* Call an application function to set up the timer that will generate
the tick interrupt. This way the application can decide which
peripheral to use. If tickless mode is used then the default
implementation defined in this file (which uses CMT0) should not be
overridden. */
configSETUP_TICK_INTERRUPT();
/* Enable the software interrupt. */
_IEN( _ICU_SWINT ) = 1;
/* Ensure the software interrupt is clear. */
_IR( _ICU_SWINT ) = 0;
/* Ensure the software interrupt is set to the kernel priority. */
_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the first task. */
prvStartFirstTask();
}
/* Execution should not reach here as the tasks are now running!
prvSetupTimerInterrupt() is called here to prevent the compiler outputting
a warning about a statically declared function not being referenced in the
case that the application writer has provided their own tick interrupt
configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
their own routine will be called in place of prvSetupTimerInterrupt()). */
prvSetupTimerInterrupt();
/* Just to make sure the function is not optimised away. */
( void ) vSoftwareInterruptISR();
/* Should not get here. */
return pdFAIL;
}
/*---------------------------------------------------------------------------*
* Routine: vApplicationSetupTimerInterrupt
*---------------------------------------------------------------------------*
* Description:
* The RX port uses this callback function to configure its tick
* interrupt. This allows the application to choose the tick interrupt
* source.
*---------------------------------------------------------------------------*/
void vApplicationSetupTimerInterrupt(void)
{
/* Enable compare match timer 0. */
MSTP( CMT0) = 0;
/* Interrupt on compare match. */
CMT0.CMCR.BIT.CMIE = 1;
/* Set the compare match value. */
CMT0.CMCOR = (unsigned short)(((PCLK_FREQUENCY / configTICK_RATE_HZ) - 1) / 8);
/* Divide the PCLK by 8. */
CMT0.CMCR.BIT.CKS = 0;
/* Enable the interrupt... */
_IEN( _CMT0_CMI0) = 1;
/* ...and set its priority to the application defined kernel priority. */
_IPR( _CMT0_CMI0) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the timer. */
CMT.CMSTR0.BIT.STR0 = 1;
}
/***********************************************************************************************************************
* Function Name: R_SWITCHES_Init
* Description : Initializes pins to be input and interrupt on switch presses.
* Arguments : detection_hz -
* The times per second that the user will call R_SWITCHES_Update(). NOTE: this is only when using
* polling mode. If you are using interrupt mode, then this argument will be ignored.
* debouce_counts -
* The number of times to check the port value before accepting the change. The slower the rate at
* which R_SWITCHES_Update() will likely lower this number.
* Return Value : none
***********************************************************************************************************************/
void R_SWITCHES_Init (uint32_t detection_hz, uint32_t debounce_counts)
{
uint32_t i;
/* The SW#_XXX defintions are common macros amongst different boards. To see the definitions for these macros
see the board defintion file. For example, this file for the RSKRX63N is rskrx63n.h. */
#if defined(MCU_RX62N) || defined(MCU_RX62T) || defined(MCU_RX621) || defined(MCU_RX610)
/* Make switch pins inputs. */
SW1_DDR = 0;
SW2_DDR = 0;
SW3_DDR = 0;
/* Enable input buffer control registers. */
SW1_ICR = 1;
SW2_ICR = 1;
SW3_ICR = 1;
#elif defined(MCU_RX63N) || defined(MCU_RX630) || defined(MCU_RX631) || defined(MCU_RX210) || defined(MCU_RX111)
/* Unlock protection register */
MPC.PWPR.BIT.B0WI = 0 ;
/* Unlock MPC registers */
MPC.PWPR.BIT.PFSWE = 1 ;
/* Make switch pins inputs. */
SW1_PDR = 0;
SW2_PDR = 0;
SW3_PDR = 0;
/* Set port mode registers for switches. */
SW1_PMR = 0;
SW2_PMR = 0;
SW3_PMR = 0;
#endif
#if SWITCHES_DETECTION_MODE == 0
#if defined(PLATFORM_BOARD_RDKRX63N)
/* The switches on the RDKRX63N are connected to the following pins/IRQ's
Switch Port IRQ
------ ---- ----
SW1 P4.0 IRQ8
SW2 P4.1 IRQ9
SW3 P4.4 IRQ12
*/
MPC.P40PFS.BYTE = 0x40; /* P40 is used as IRQ pin */
MPC.P41PFS.BYTE = 0x40; /* P40 is used as IRQ pin */
MPC.P44PFS.BYTE = 0x40; /* P40 is used as IRQ pin */
#elif defined(PLATFORM_BOARD_RSKRX63N)
/* The switches on the RSKRX63N are connected to the following pins/IRQ's
Switch Port IRQ
------ ---- ----
SW1 P3.2 IRQ2
SW2 P0.0 IRQ8
SW3 P0.7 IRQ15
*/
MPC.P32PFS.BYTE = 0x40; /* P32 is used as IRQ pin */
MPC.P00PFS.BYTE = 0x40; /* P00 is used as IRQ pin */
MPC.P07PFS.BYTE = 0x40; /* P07 is used as IRQ pin */
#elif defined(PLATFORM_BOARD_RSKRX630)
/* The switches on the RSKRX630 are connected to the following pins/IRQ's
Switch Port IRQ
------ ---- ----
SW1 P3.2 IRQ2
SW2 P4.4 IRQ12
SW3 P0.7 IRQ15
*/
MPC.P32PFS.BYTE = 0x40; /* P32 is used as IRQ pin */
MPC.P44PFS.BYTE = 0x40; /* P44 is used as IRQ pin */
MPC.P07PFS.BYTE = 0x40; /* P07 is used as IRQ pin */
#elif defined(PLATFORM_BOARD_RSKRX62N)
/* The switches on the RSKRX62N are connected to the following pins/IRQ's
Switch Port IRQ
------ ---- ----
SW1 P0.0 IRQ8-A
SW2 P0.1 IRQ9-A
SW3 P0.7 IRQ15-A
*/
IOPORT.PF8IRQ.BIT.ITS8 = 0; /* IRQ8-A pin is used. */
IOPORT.PF8IRQ.BIT.ITS9 = 0; /* IRQ9-A pin is used. */
IOPORT.PF8IRQ.BIT.ITS15 = 0; /* IRQ15-A pin is used. */
#elif defined(PLATFORM_BOARD_RDKRX62N)
/* The switches on the RDKRX62N are connected to the following pins/IRQ's
Switch Port IRQ
------ ---- ----
SW1 P4.0 IRQ8
SW2 P4.1 IRQ9
SW3 P4.2 IRQ10
*/
/* Nothing else needed to do here since RDK has 100-pin package and there are no alternate pins to choose. */
#elif defined(PLATFORM_BOARD_RSKRX62T)
/* The switches on the RSKRX62T are connected to the following pins/IRQ's
Switch Port IRQ
------ ---- ----
SW1 PE.5 IRQ0-B
SW2 PE.4 IRQ1-B
SW3 PB.4 IRQ3
*/
IOPORT.PF8IRQ.BIT.ITS0 = 1; /* IRQ0-B pin is used. */
IOPORT.PF8IRQ.BIT.ITS1 = 1; /* IRQ1-B pin is used. */
/* IRQ3 is only on 1 pin. */
#elif defined(PLATFORM_BOARD_RSKRX610)
/* The switches on the RSKRX610 are connected to the following pins/IRQ's
Switch Port IRQ
------ ---- ----
SW1 P0.0 IRQ8-A
SW2 P0.1 IRQ9-A
SW3 P1.3 IRQ3-B
*/
IOPORT.PFCR8.BIT.ITS8 = 0; /* IRQ8-A pin is used. */
IOPORT.PFCR8.BIT.ITS9 = 0; /* IRQ9-A pin is used. */
IOPORT.PFCR9.BIT.ITS3 = 1; /* IRQ3-B pin is used. */
/* Enable IRQ detection. */
ICU.IRQER[SW1_IRQ_NUMBER].BIT.IRQEN = 1;
ICU.IRQER[SW2_IRQ_NUMBER].BIT.IRQEN = 1;
ICU.IRQER[SW3_IRQ_NUMBER].BIT.IRQEN = 1;
#elif defined(PLATFORM_BOARD_RSKRX210)
/* The switches on the RSKRX210 are connected to the following pins/IRQ's
Switch Port IRQ
------ ---- ----
SW1 P3.1 IRQ1
SW2 P3.3 IRQ3
SW3 P3.4 IRQ4
*/
MPC.P31PFS.BYTE = 0x40; /* P31 is used as IRQ pin */
MPC.P33PFS.BYTE = 0x40; /* P33 is used as IRQ pin */
MPC.P34PFS.BYTE = 0x40; /* P34 is used as IRQ pin */
#elif defined(PLATFORM_BOARD_RSKRX111)
/* The switches on the RSKRX210 are connected to the following pins/IRQ's
Switch Port IRQ
------ ---- ----
SW1 P3.0 IRQ0
SW2 P3.1 IRQ1
SW3 PE.4 IRQ4
*/
MPC.P30PFS.BYTE = 0x40; /* P30 is used as IRQ pin */
MPC.P31PFS.BYTE = 0x40; /* P31 is used as IRQ pin */
MPC.PE4PFS.BYTE = 0x40; /* PE4 is used as IRQ pin */
#endif
/* Set IRQ type (falling edge) */
ICU.IRQCR[SW1_IRQ_NUMBER].BIT.IRQMD = 0x01;
ICU.IRQCR[SW2_IRQ_NUMBER].BIT.IRQMD = 0x01;
ICU.IRQCR[SW3_IRQ_NUMBER].BIT.IRQMD = 0x01;
/* Set interrupt priorities which muse be below
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
_IPR( X_IRQ(SW1_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
_IPR( X_IRQ(SW2_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
_IPR( X_IRQ(SW3_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
/* Clear any pending interrupts */
_IR( X_IRQ(SW1_IRQ_NUMBER) ) = 0;
_IR( X_IRQ(SW2_IRQ_NUMBER) ) = 0;
_IR( X_IRQ(SW3_IRQ_NUMBER) ) = 0;
/* Enable the interrupts */
_IEN( X_IRQ(SW1_IRQ_NUMBER) ) = 1;
_IEN( X_IRQ(SW2_IRQ_NUMBER) ) = 1;
_IEN( X_IRQ(SW3_IRQ_NUMBER) ) = 1;
#else
/* This is based upon having 3 counts at 10Hz. */
g_sw_debounce_cnts = debounce_counts;
/* Init debounce structures. */
for (i = 0; i < SWITCHES_NUM; i++)
{
g_switches[i].active = false;
g_switches[i].debounce_cnt = 0;
}
#endif /* SWITCHES_DETECTION_MODE */
}