/**
* @brief DeInitializes the CEC peripheral
* @param hcec CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
if(hcec == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
hcec->gState = HAL_CEC_STATE_BUSY;
/* DeInit the low level hardware */
HAL_CEC_MspDeInit(hcec);
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Clear Flags */
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
/* Disable the following CEC Transmission/Reception interrupts as
* well as the following CEC Transmission/Reception Errors interrupts
* Rx Byte Received IT
* End of Reception IT
* Rx overrun
* Rx bit rising error
* Rx short bit period error
* Rx long bit period error
* Rx missing acknowledge
* Tx Byte Request IT
* End of Transmission IT
* Tx Missing Acknowledge IT
* Tx-Error IT
* Tx-Buffer Underrun IT
* Tx arbitration lost */
__HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_RESET;
hcec->RxState = HAL_CEC_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hcec);
return HAL_OK;
}
/**
* @brief Initializes the CEC mode according to the specified
* parameters in the CEC_InitTypeDef and creates the associated handle .
* @param hcec: CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(hcec->Init.TimingErrorFree));
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(hcec->Init.PeriodErrorFree));
assert_param(IS_CEC_ADDRESS(hcec->Init.OwnAddress));
if(hcec->gState == HAL_CEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
HAL_CEC_MspInit(hcec);
}
hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Write to CEC Control Register */
MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree | hcec->Init.PeriodErrorFree);
/* Write to CEC Own Address Register */
MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
/* Configure the prescaler to generate the required 50 microseconds time base.*/
MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50U * (HAL_RCC_GetPCLK1Freq()/1000000U) - 1U);
/* Enable the following CEC Interrupt */
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
/* Enable the CEC Peripheral */
__HAL_CEC_ENABLE(hcec);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_READY;
hcec->RxState = HAL_CEC_STATE_READY;
return HAL_OK;
}
/**
* @brief Receive data in interrupt mode.
* @param hcec: CEC handle
* @param pData: pointer to received data buffer.
* Note that the received data size is not known beforehand, the latter is known
* when the reception is complete and is stored in hcec->RxXferSize.
* hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
* If only a header is received, hcec->RxXferSize = 0
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
{
if(hcec->State == HAL_CEC_STATE_READY)
{
if(pData == NULL )
{
hcec->State = HAL_CEC_STATE_ERROR;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hcec);
hcec->RxXferSize = 0;
hcec->pRxBuffPtr = pData;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* the IP is moving to a ready to receive state */
hcec->State = HAL_CEC_STATE_STANDBY_RX;
/* Disable Peripheral to write CEC_IER register */
__HAL_CEC_DISABLE(hcec);
/* Enable the following CEC Reception Error Interrupts:
* Rx overrun
* Rx bit rising error
* Rx short bit period error
* Rx long bit period error
* Rx missing acknowledge */
__HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
/* Process Unlocked */
__HAL_UNLOCK(hcec);
/* Enable the following two CEC Reception interrupts:
* Rx Byte Received IT
* End of Reception IT */
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
__HAL_CEC_ENABLE(hcec);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Initializes the Own Address of the CEC device
* @param hcec: CEC handle
* @param CEC_OwnAddress: The CEC own address.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
{
/* Check the parameters */
assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
{
/* Process Locked */
__HAL_LOCK(hcec);
hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
{
hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U);
}
else
{
hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
}
hcec->gState = HAL_CEC_STATE_READY;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief DeInitializes the CEC peripheral
* @param hcec: CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
if(hcec == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
hcec->State = HAL_CEC_STATE_BUSY;
/* Set peripheral to reset state */
hcec->Instance->CFGR = 0x0;
hcec->Instance->OAR = 0x0;
hcec->Instance->PRES = 0x0;
hcec->Instance->CFGR = 0x0;
hcec->Instance->ESR = 0x0;
hcec->Instance->CSR = 0x0;
hcec->Instance->TXD = 0x0;
hcec->Instance->RXD = 0x0;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* DeInit the low level hardware */
HAL_CEC_MspDeInit(hcec);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->State = HAL_CEC_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hcec);
return HAL_OK;
}
/**
* @brief Initializes the CEC mode according to the specified
* parameters in the CEC_InitTypeDef and creates the associated handle .
* @param hcec: CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
if(hcec->gState == HAL_CEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
HAL_CEC_MspInit(hcec);
}
hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Write to CEC Control Register */
hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
hcec->Init.ListenMode;
/* Enable the following CEC Transmission/Reception interrupts as
* well as the following CEC Transmission/Reception Errors interrupts
* Rx Byte Received IT
* End of Reception IT
* Rx overrun
* Rx bit rising error
* Rx short bit period error
* Rx long bit period error
* Rx missing acknowledge
* Tx Byte Request IT
* End of Transmission IT
* Tx Missing Acknowledge IT
* Tx-Error IT
* Tx-Buffer Underrun IT
* Tx arbitration lost */
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
/* Enable the CEC Peripheral */
__HAL_CEC_ENABLE(hcec);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_READY;
hcec->RxState = HAL_CEC_STATE_READY;
return HAL_OK;
}
/**
* @brief Send data in interrupt mode
* @param hcec: CEC handle.
* Function called under interruption only, once
* interruptions have been enabled by HAL_CEC_Transmit_IT()
* @retval HAL status
*/
static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
{
/* if the IP is already busy or if there is a previous transmission
already pending due to arbitration loss */
if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
|| (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
{
__HAL_LOCK(hcec);
/* set state to BUSY TX, in case it wasn't set already (case
* of transmission new attempt after arbitration loss) */
if (hcec->State != HAL_CEC_STATE_BUSY_TX)
{
hcec->State = HAL_CEC_STATE_BUSY_TX;
}
/* if all data have been sent */
if(hcec->TxXferCount == 0)
{
/* Disable Peripheral to write CEC_IER register */
__HAL_CEC_DISABLE(hcec);
/* Disable the CEC Transmission Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
/* Disable the CEC Transmission Error Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
hcec->State = HAL_CEC_STATE_READY;
/* Call the Process Unlocked before calling the Tx call back API to give the possibility to
start again the Transmission under the Tx call back API */
__HAL_UNLOCK(hcec);
HAL_CEC_TxCpltCallback(hcec);
return HAL_OK;
}
else
{
if (hcec->TxXferCount == 1)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
hcec->TxXferCount--;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send data in interrupt mode
* @param hcec: CEC handle
* @param DestinationAddress: destination logical address
* @param pData: pointer to input byte data buffer
* @param Size: amount of data to be sent in bytes (without counting the header).
* 0 means only the header is sent (ping operation).
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
{
uint8_t temp = 0;
/* if the IP isn't already busy and if there is no previous transmission
already pending due to arbitration lost */
if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
&& (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
{
if((pData == NULL ) && (Size > 0))
{
hcec->State = HAL_CEC_STATE_ERROR;
return HAL_ERROR;
}
assert_param(IS_CEC_ADDRESS(DestinationAddress));
assert_param(IS_CEC_MSGSIZE(Size));
/* Process Locked */
__HAL_LOCK(hcec);
hcec->pTxBuffPtr = pData;
hcec->State = HAL_CEC_STATE_BUSY_TX;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* Disable Peripheral to write CEC_IER register */
__HAL_CEC_DISABLE(hcec);
/* Enable the following two CEC Transmission interrupts as
* well as the following CEC Transmission Errors interrupts:
* Tx Byte Request IT
* End of Transmission IT
* Tx Missing Acknowledge IT
* Tx-Error IT
* Tx-Buffer Underrun IT
* Tx arbitration lost */
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
/* initialize the number of bytes to send,
* 0 means only one header is sent (ping operation) */
hcec->TxXferCount = Size;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
/* in case of no payload (Size = 0), sender is only pinging the system;
* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
if (Size == 0)
{
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* send header block */
temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
hcec->Instance->TXDR = temp;
/* Set TX Start of Message (TXSOM) bit */
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
return HAL_OK;
}
/* if the IP is already busy or if there is a previous transmission
already pending due to arbitration loss */
else if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
|| (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
{
__HAL_LOCK(hcec);
/* set state to BUSY TX, in case it wasn't set already (case
* of transmission new attempt after arbitration loss) */
if (hcec->State != HAL_CEC_STATE_BUSY_TX)
{
hcec->State = HAL_CEC_STATE_BUSY_TX;
}
/* if all data have been sent */
if(hcec->TxXferCount == 0)
{
/* Disable Peripheral to write CEC_IER register */
__HAL_CEC_DISABLE(hcec);
/* Disable the CEC Transmission Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
/* Disable the CEC Transmission Error Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND);
hcec->State = HAL_CEC_STATE_READY;
/* Call the Process Unlocked before calling the Tx call back API to give the possibility to
start again the Transmission under the Tx call back API */
__HAL_UNLOCK(hcec);
HAL_CEC_TxCpltCallback(hcec);
return HAL_OK;
}
else
{
if (hcec->TxXferCount == 1)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
hcec->TxXferCount--;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send data in interrupt mode
* @param hcec: CEC handle.
* Function called under interruption only, once
* interruptions have been enabled by HAL_CEC_Transmit_IT()
* @retval HAL status
*/
static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
{
/* if the IP is already busy or if there is a previous transmission
already pending due to arbitration loss */
if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
|| (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
{
/* set state to BUSY TX, in case it wasn't set already (case
* of transmission new attempt after arbitration loss) */
if (hcec->State != HAL_CEC_STATE_BUSY_TX)
{
hcec->State = HAL_CEC_STATE_BUSY_TX;
}
/* if all data have been sent */
if(hcec->TxXferCount == 0)
{
/* Disable Peripheral to write CEC_IER register */
__HAL_CEC_DISABLE(hcec);
/* Disable the CEC Transmission Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
/* Disable the CEC Transmission Error Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
/* If RX interruptions are enabled, return to HAL_CEC_STATE_STANDBY_RX state */
if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IT_RXBR|CEC_IT_RXEND) ) != RESET)
{
hcec->State = HAL_CEC_STATE_STANDBY_RX;
}
else
{
hcec->State = HAL_CEC_STATE_READY;
}
HAL_CEC_TxCpltCallback(hcec);
return HAL_OK;
}
else
{
if (hcec->TxXferCount == 1)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
hcec->TxXferCount--;
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
