/** * @brief Close the receiver path * @param None * @retval None */ static void ReceiveClosure(void) { /* * Disable both DMA */ __HAL_DMA_DISABLE(SPI_Context.hspi->hdmatx); __HAL_DMA_DISABLE(SPI_Context.hspi->hdmarx); /* * Check if a command is pending */ __disable_irq(); if(SPI_Context.SPI_Transmit_Context.RequestPending == TRUE) { SPI_Context.SPI_Transmit_Context.RequestPending = FALSE; SPI_Context.Spi_Peripheral_State = SPI_BUSY; Disable_SPI_Receiving_Path(); __enable_irq(); WakeupBlueNRG(); } else { SPI_Context.Spi_Peripheral_State = SPI_AVAILABLE; __enable_irq(); } return; }
/** * @brief Resumes the audio stream playing from the Media. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) { /* Process Locked */ __HAL_LOCK(hi2s); /* Disable the I2S Tx/Rx DMA requests */ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); /* Abort the I2S DMA Channel tx */ if(hi2s->hdmatx != NULL) { /* Disable the I2S DMA channel */ __HAL_DMA_DISABLE(hi2s->hdmatx); HAL_DMA_Abort(hi2s->hdmatx); } /* Abort the I2S DMA Channel rx */ if(hi2s->hdmarx != NULL) { /* Disable the I2S DMA channel */ __HAL_DMA_DISABLE(hi2s->hdmarx); HAL_DMA_Abort(hi2s->hdmarx); } /* Disable I2S peripheral */ __HAL_I2S_DISABLE(hi2s); hi2s->State = HAL_I2S_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2s); return HAL_OK; }
/** * @brief Close the transmit mechanism after packet has been sent * Wait for the event to come back * @param None * @retval None */ static void TransmitClosure(void) { LPM_Mode_Request(eLPM_SPI_TX, eLPM_Mode_LP_Stop); SPI_Context.Spi_Peripheral_State = SPI_AVAILABLE; Disable_SPI_CS(); /* * Disable both DMA */ __HAL_DMA_DISABLE(SPI_Context.hspi->hdmatx); __HAL_DMA_DISABLE(SPI_Context.hspi->hdmarx); Enable_SPI_Receiving_Path(); return; }
/** * @brief Starts the multi_buffer DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) { /* Process Locked */ __HAL_LOCK(hdma); /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == 0) { hdma->State = HAL_DMA_STATE_BUSY_MEM0; } /* Current memory buffer used is Memory 1 */ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) { hdma->State = HAL_DMA_STATE_BUSY_MEM1; } /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Enable the double buffer mode */ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; /* Configure DMA Stream destination address */ hdma->Instance->M1AR = SecondMemAddress; /* Configure the source, destination address and the data length */ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the peripheral */ __HAL_DMA_ENABLE(hdma); return HAL_OK; }
/** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Process locked */ __HAL_LOCK(hdma); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable all interrupts */ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME; hdma->Instance->FCR |= DMA_IT_FE; /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); return HAL_OK; }
uint32_t uart_send_bytes(uint8_t* pData, uint16_t len) { /* Wait until previous tx is done */ uint32_t tickstart = HAL_GetTick(); while ((uart_data.TxState == UART_TRANSMITTING) && ((HAL_GetTick() - tickstart) < UART_TXDATA_TIMEOUT_MS)); if (uart_data.TxState == UART_TRANSMITTING) { return 0; } __HAL_DMA_DISABLE(&DMAhandle_TX); /* Set source address and buffer length */ DMAhandle_TX.Instance->M0AR = (uint32_t) pData; DMAhandle_TX.Instance->NDTR = (uint16_t) len; /* Enable transfer complete interrupt */ __HAL_DMA_ENABLE_IT(&DMAhandle_TX, DMA_IT_TC); /* Enable UART as DMA enabled transmitter */ UARThandle.Instance->CR3 |= USART_CR3_DMAT; uart_data.TxState = UART_TRANSMITTING; __HAL_DMA_ENABLE(&DMAhandle_TX); return (uint32_t) len; }
/** * @brief Abort the DMA Transfer. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if(HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; status = HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); } return status; }
/** * @brief Start the DMA Transfer. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if(HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); status = HAL_BUSY; } return status; }
/** * @brief Suspends the Camera capture. * @param None * @retval None */ void BSP_CAMERA_Suspend(void) { /* Disable the DMA */ __HAL_DMA_DISABLE(hdcmi_eval.DMA_Handle); /* Disable the DCMI */ __HAL_DCMI_DISABLE(&hdcmi_eval); }
/** * @brief Aborts the DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * * @note After disabling a DMA Stream, a check for wait until the DMA Stream is * effectively disabled is added. If a Stream is disabled * while a data transfer is ongoing, the current data will be transferred * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; uint32_t tickstart = HAL_GetTick(); if(hdma->State != HAL_DMA_STATE_BUSY) { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); hdma->Instance->FCR &= ~(DMA_IT_FE); if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) { hdma->Instance->CR &= ~(DMA_IT_HT); } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; return HAL_TIMEOUT; } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; } return HAL_OK; }
/** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Process locked */ __HAL_LOCK(hdma); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the transfer complete interrupt */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); /* Enable the Half transfer complete interrupt */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); /* Enable the transfer Error interrupt */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); return HAL_OK; }
/** * @brief DeInitializes the DMA peripheral * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) { return HAL_ERROR; } /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { /* Return error status */ return HAL_BUSY; } /* Check the parameters */ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Streamx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Streamx control register */ hdma->Instance->CR = 0U; /* Reset DMA Streamx number of data to transfer register */ hdma->Instance->NDTR = 0U; /* Reset DMA Streamx peripheral address register */ hdma->Instance->PAR = 0U; /* Reset DMA Streamx memory 0 address register */ hdma->Instance->M0AR = 0U; /* Reset DMA Streamx memory 1 address register */ hdma->Instance->M1AR = 0U; /* Reset DMA Streamx FIFO control register */ hdma->Instance->FCR = (uint32_t)0x00000021U; /* Get DMA steam Base Address */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; }
/** * @brief DeInitialize the DMA peripheral. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ if(hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Channel control register */ hdma->Instance->CCR = 0; /* Calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Reset DMA channel selection register */ if (DMA1 == hdma->DmaBaseAddress) { /* DMA1 */ DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); } else { /* DMA2 */ DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; }
/** * @brief Manage the SPI transmit * @param TransmitRequest: the transmit request * @retval None */ static void SPI_Transmit_Manager(SPI_TRANSMIT_REQUEST_t TransmitRequest) { /* * Disable both DMA */ __HAL_DMA_DISABLE(SPI_Context.hspi->hdmatx); __HAL_DMA_DISABLE(SPI_Context.hspi->hdmarx); __HAL_DMA_DISABLE_IT(SPI_Context.hspi->hdmarx, DMA_IT_TC); /**< Disable Receive packet notification */ __HAL_DMA_CLEAR_FLAG(SPI_Context.hspi->hdmatx, BNRG_SPI_TX_DMA_TC_FLAG); /**< Clear flag in DMA */ HAL_NVIC_ClearPendingIRQ(BNRG_SPI_DMA_TX_IRQn); /**< Clear DMA pending bit in NVIC */ __HAL_DMA_ENABLE_IT(SPI_Context.hspi->hdmatx, DMA_IT_TC); /**< Enable Transmit packet notification */ __HAL_BLUENRG_DMA_SET_MINC(SPI_Context.hspi->hdmatx); /**< Configure DMA to send Tx packet */ switch (TransmitRequest) { case SPI_HEADER_TRANSMIT: SPI_Context.SPI_Transmit_Context.Spi_Transmit_Event = SPI_HEADER_TRANSMITTED; #ifdef ENABLE_SPI_FIX set_irq_as_input(); #endif __HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmatx, SPI_Context.SPI_Transmit_Context.header_size); /**< Set counter in DMA TX */ __HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmatx, (uint32_t)SPI_Context.SPI_Transmit_Context.header_data); /**< Set memory address in DMA TX */ break; case SPI_PAYLOAD_TRANSMIT: SPI_Context.SPI_Transmit_Context.Spi_Transmit_Event = SPI_PAYLOAD_TRANSMITTED; __HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmatx, SPI_Context.SPI_Transmit_Context.payload_size_to_transmit); /**< Set counter in DMA TX */ __HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmatx, (uint32_t)SPI_Context.SPI_Transmit_Context.payload_data); /**< Set memory address in DMA TX */ break; default: break; } __HAL_DMA_ENABLE(SPI_Context.hspi->hdmatx); /**< Enable DMA TX */ }
/** * @brief DeInitializes the DMA peripheral * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef _HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA peripheral state */ if(hdma == NULL) { return HAL_ERROR; } /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { return HAL_ERROR; } /* Disable the selected DMA Streamx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Streamx control register */ hdma->Instance->CR = 0; /* Reset DMA Streamx number of data to transfer register */ hdma->Instance->NDTR = 0; /* Reset DMA Streamx peripheral address register */ hdma->Instance->PAR = 0; /* Reset DMA Streamx memory 0 address register */ hdma->Instance->M0AR = 0; /* Reset DMA Streamx memory 1 address register */ hdma->Instance->M1AR = 0; /* Reset DMA Streamx FIFO control register */ hdma->Instance->FCR = (uint32_t)0x00000021; /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; }
/** * @brief stop the audio stream receive from the Media. * @param hspdif: SPDIFRX handle * @retval None */ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) { /* Process Locked */ __HAL_LOCK(hspdif); /* Disable the SPDIFRX DMA requests */ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); /* Disable the SPDIFRX DMA channel */ __HAL_DMA_DISABLE(hspdif->hdmaDrRx); __HAL_DMA_DISABLE(hspdif->hdmaCsRx); /* Disable SPDIFRX peripheral */ __HAL_SPDIFRX_IDLE(hspdif); hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); return HAL_OK; }
/** * @brief DeInitializes the DMA peripheral * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ if(hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { return HAL_ERROR; } /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Channel control register */ hdma->Instance->CCR = 0; /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0; /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0; /* Reset DMA Channel memory address register */ hdma->Instance->CMAR = 0; /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; }
/** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if(HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Remain BUSY */ status = HAL_BUSY; } return status; }
/** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static HAL_StatusTypeDef MBED_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Process locked */ __HAL_LOCK(hdma); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length */ /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; } else { /* Memory to Peripheral */ /* Configure DMA Stream source address */ hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } /* Enable all interrupts EXCEPT HALF TRANSFER COMPLETE */ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; hdma->Instance->FCR |= DMA_IT_FE; /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); return HAL_OK; }
/** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Process locked */ __HAL_LOCK(hdma); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); <<<<<<< HEAD:source/stm32f4xx_hal_dma__FIX.c
/** * @brief Aborts the DMA Transfer in Interrupt mode. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { if(hdma->State != HAL_DMA_STATE_BUSY) { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; return HAL_ERROR; } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; /* Disable the stream */ __HAL_DMA_DISABLE(hdma); } return HAL_OK; }
/** * @brief Abort the DMA Transfer. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return status; }
/** * @brief Aborts the DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * * @note After disabling a DMA Stream, a check for wait until the DMA Stream is * effectively disabled is added. If a Stream is disabled * while a data transfer is ongoing, the current data will be transferred * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { uint32_t timeout = 0x00; /* Disable the stream */ __HAL_DMA_DISABLE(hdma); /* Get timeout */ timeout = HAL_GetTick() + HAL_TIMEOUT_DMA_ABORT; /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != 0) { /* Check for the Timeout */ if(HAL_GetTick() >= timeout) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; return HAL_TIMEOUT; } } /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; return HAL_OK; }
/** * @brief Aborts the DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * * @note After disabling a DMA Channel, a check for wait until the DMA Channel is * effectively disabled is added. If a Channel is disabled * while a data transfer is ongoing, the current data will be transferred * and the Channel will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { uint32_t tickstart = 0x00; /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DMA Channel is effectively disabled */ while((hdma->Instance->CCR & DMA_CCR_EN) != 0) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_TIMEOUT; } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_OK; }
/** * @brief Aborts the DMA Transfer in Interrupt mode. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if(HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; status = HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); } } return status; }
/** * @brief Handles DMA interrupt request. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { uint32_t tmpisr; __IO uint32_t count = 0; uint32_t timeout = SystemCoreClock / 9600; /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; tmpisr = regs->ISR; /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) { if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); } } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); } if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; if(HAL_DMA_STATE_ABORT == hdma->State) { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); hdma->Instance->FCR &= ~(DMA_IT_FE); if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) { hdma->Instance->CR &= ~(DMA_IT_HT); } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; if(hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); } return; } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) { if(hdma->XferM1CpltCallback != NULL) { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); } } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; } if(hdma->XferCpltCallback != NULL) { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); } } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) { hdma->State = HAL_DMA_STATE_ABORT; /* Disable the stream */ __HAL_DMA_DISABLE(hdma); do { if (++count > timeout) { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; } if(hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } }
void UART_RestartDMA(void) { __HAL_DMA_DISABLE(&hdma_usart1_rx); hdma_usart1_rx.Instance->CNDTR = BUFFER_SIZE; __HAL_DMA_ENABLE(&hdma_usart1_rx); }
/** * @brief DeInitializes the DMA peripheral * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { return HAL_ERROR; } /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Channel control register */ hdma->Instance->CCR = 0; /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0; /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0; /* Reset DMA Channel memory address register */ hdma->Instance->CMAR = 0; /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Reset DMA channel selection register */ if (hdma->Instance == DMA1_Channel1) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S; } else if (hdma->Instance == DMA1_Channel2) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S; } else if (hdma->Instance == DMA1_Channel3) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S; } else if (hdma->Instance == DMA1_Channel4) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S; } else if (hdma->Instance == DMA1_Channel5) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S; } else if (hdma->Instance == DMA1_Channel6) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S; } else if (hdma->Instance == DMA1_Channel7) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S; } /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; }
/** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp = 0U; uint32_t tickstart = HAL_GetTick(); DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); /* Check the memory burst, peripheral burst and FIFO threshold parameters only when FIFO mode is enabled */ if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) { assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Allocate lock resource */ __HAL_UNLOCK(hdma); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; return HAL_TIMEOUT; } } /* Get the CR register value */ tmp = hdma->Instance->CR; /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority; /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; /* Get the FCR register value */ tmp = hdma->Instance->FCR; /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; if (DMA_CheckFifoParam(hdma) != HAL_OK) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; return HAL_ERROR; } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; return HAL_OK; }
/** * @brief DeInitialize the DMA peripheral. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ if(hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Channel control register */ hdma->Instance->CCR = 0U; /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0U; /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0U; /* Reset DMA Channel memory address register */ hdma->Instance->CMAR = 0U; #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */ /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); /* Clean all callbacks */ hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; /* Reset the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Reset the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; }