/** * @brief Receive an amount of data (Control Flow) with Interrupt * @param hspdif: SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) { /* Receive data */ (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR; hspdif->CsXferCount--; if(hspdif->CsXferCount == 0) { /* Disable CSRNE interrupt */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); HAL_SPDIFRX_CxCpltCallback(hspdif); } }
/** * @brief Receive an amount of data (Data Flow) with Interrupt * @param hspdif: SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) { /* Receive data */ (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR; hspdif->RxXferCount--; if(hspdif->RxXferCount == 0) { /* Disable RXNE/PE and OVR interrupts */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); HAL_SPDIFRX_RxCpltCallback(hspdif); } }
/** * @brief This function handles SPDIFRX Communication Timeout. * @param hspdif: SPDIFRX handle * @param Flag: Flag checked * @param Status: Value of the flag expected * @param Timeout: Duration of the timeout * @param tickstart: Tick start value * @retval HAL status */ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart) { /* Wait until flag is set */ if(Status == RESET) { while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); hspdif->State= HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); return HAL_TIMEOUT; } } } } else { while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); hspdif->State= HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); return HAL_TIMEOUT; } } } } return HAL_OK; }
/** * @brief Receive an amount of data (Control Flow) with DMA * @param hspdif SPDIFRX handle * @param pData a 32-bit pointer to the Receive data buffer. * @param Size number of data (Control Flow) sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) { hspdif->pCsBuffPtr = pData; hspdif->CsXferSize = Size; hspdif->CsXferCount = Size; /* Process Locked */ __HAL_LOCK(hspdif); hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; /* Set the SPDIFRX Rx DMA Half transfer complete callback */ hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt; /* Set the SPDIFRX Rx DMA transfer complete callback */ hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt; /* Set the DMA error callback */ hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size); /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); /* Wait until SYNCD flag is set */ do { if (count-- == 0U) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); hspdif->State= HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); return HAL_TIMEOUT; } } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); /* Start reception */ __HAL_SPDIFRX_RCV(hspdif); } /* Process Unlocked */ __HAL_UNLOCK(hspdif); return HAL_OK; } else { return HAL_BUSY; } }
/** * @brief Receive an amount of data (Control Flow) with Interrupt * @param hspdif SPDIFRX handle * @param pData a 32-bit pointer to the Receive data buffer. * @param Size number of data sample (Control Flow) to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hspdif); hspdif->pCsBuffPtr = pData; hspdif->CsXferSize = Size; hspdif->CsXferCount = Size; hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; /* Check if a receive process is ongoing or not */ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; /* Enable the SPDIFRX PE Error Interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); /* Enable the SPDIFRX OVR Error Interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); /* Process Unlocked */ __HAL_UNLOCK(hspdif); /* Enable the SPDIFRX CSRNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); /* Wait until SYNCD flag is set */ do { if (count-- == 0U) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); hspdif->State= HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); return HAL_TIMEOUT; } } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); /* Start reception */ __HAL_SPDIFRX_RCV(hspdif); } return HAL_OK; } else { return HAL_BUSY; } }