/* Do structure specific swaps if Eeprom format is non native to host */
static void
eepromSwap(struct ar5416eeprom *ee)
{
uint32_t integer, i, j;
uint16_t word;
MODAL_EEP_HEADER *pModal;
/* convert Base Eep header */
word = __bswap16(ee->baseEepHeader.length);
ee->baseEepHeader.length = word;
word = __bswap16(ee->baseEepHeader.checksum);
ee->baseEepHeader.checksum = word;
word = __bswap16(ee->baseEepHeader.version);
ee->baseEepHeader.version = word;
word = __bswap16(ee->baseEepHeader.regDmn[0]);
ee->baseEepHeader.regDmn[0] = word;
word = __bswap16(ee->baseEepHeader.regDmn[1]);
ee->baseEepHeader.regDmn[1] = word;
word = __bswap16(ee->baseEepHeader.rfSilent);
ee->baseEepHeader.rfSilent = word;
word = __bswap16(ee->baseEepHeader.blueToothOptions);
ee->baseEepHeader.blueToothOptions = word;
word = __bswap16(ee->baseEepHeader.deviceCap);
ee->baseEepHeader.deviceCap = word;
/* convert Modal Eep header */
for (j = 0; j < 2; j++) {
pModal = &ee->modalHeader[j];
/* XXX linux/ah_osdep.h only defines __bswap32 for BE */
integer = __bswap32(pModal->antCtrlCommon);
pModal->antCtrlCommon = integer;
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
integer = __bswap32(pModal->antCtrlChain[i]);
pModal->antCtrlChain[i] = integer;
}
for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
word = __bswap16(pModal->spurChans[i].spurChan);
pModal->spurChans[i].spurChan = word;
}
}
}
u_int32_t ieee80211_aow_tx_ctrl(u_int8_t* data, u_int32_t datalen, u_int64_t tsf)
{
aow_ctrl_data_msg_t* pd = NULL;
struct ieee80211_node *ni = NULL;
struct ieee80211com *ic = aowinfo.ic;
int is_cmd_local;
u_int32_t cmd = 0;
u_int8_t event_subtype = CM_SEND_BUFFER_STATUS_FAIL;
aow_ctrl_msg_t* mh = (aow_ctrl_msg_t*)data;
is_cmd_local = IS_AOW_CTRL_MSG_LOCAL(mh);
cmd = get_ctrl_msg_cmd_type(mh);
/*
* The command is meant for this device,
* pass it to athcm connection manager
*/
if (is_cmd_local) {
aow_ci_send(ic, data, datalen);
return 0;
}
pd = (aow_ctrl_data_msg_t*)(mh->data);
ni = ieee80211_find_node(&ic->ic_sta, pd->addr);
if (ni) {
ieee80211_send_aow_ctrl_ipformat(ni, pd->data, __bswap32(pd->length) , 0, tsf, 0, 0);
event_subtype = CM_SEND_BUFFER_STATUS_PASS;
}
ieee80211_aow_send_to_host(ic, &event_subtype, sizeof(event_subtype), AOW_HOST_PKT_EVENT, event_subtype, NULL);
return 0;
}
HAL_BOOL
ar5416FillTxDesc(struct ath_hal *ah, void *ds, dma_addr_t *bufAddr,
u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE keyType, HAL_BOOL first_seg,
HAL_BOOL last_seg, const void *ds0)
{
struct ar5416_desc *ads = AR5416DESC(ds);
HALASSERT((seg_len[0] &~ AR_BufLen) == 0);
OS_MEMZERO(&(ads->u.tx.tx_status), sizeof(ads->u.tx.tx_status));
/* Set the buffer addresses */
ads->ds_data = bufAddr[0];
if (first_seg) {
/*
* First descriptor, don't clobber xmit control data
* setup by ar5416SetupTxDesc.
*/
ads->ds_ctl1 |= seg_len[0] | (last_seg ? 0 : AR_TxMore);
} else if (last_seg) { /* !first_seg && last_seg */
/*
* Last descriptor in a multi-descriptor frame,
* copy the multi-rate transmit parameters from
* the first frame for processing on completion.
*/
ads->ds_ctl0 = 0;
ads->ds_ctl1 = seg_len[0];
#ifdef AH_NEED_DESC_SWAP
ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2);
ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3);
#else
ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
#endif
} else { /* !first_seg && !last_seg */
/*
* Intermediate descriptor in a multi-descriptor frame.
*/
ads->ds_ctl0 = 0;
ads->ds_ctl1 = seg_len[0] | AR_TxMore;
ads->ds_ctl2 = 0;
ads->ds_ctl3 = 0;
}
return AH_TRUE;
}
/* Swap transmit descriptor */
static __inline void
ar5416SwapTxDesc(void *ds)
{
ds->ds_data = __bswap32(ds->ds_data);
ds->ds_ctl0 = __bswap32(ds->ds_ctl0);
ds->ds_ctl1 = __bswap32(ds->ds_ctl1);
ds->ds_hw[0] = __bswap32(ds->ds_hw[0]);
ds->ds_hw[1] = __bswap32(ds->ds_hw[1]);
ds->ds_hw[2] = __bswap32(ds->ds_hw[2]);
ds->ds_hw[3] = __bswap32(ds->ds_hw[3]);
}
static void swapData(struct zsDmaDesc* usbDesc)
{
int len = (usbDesc->dataSize & 0xfffffffc) >> 2;
int i;
A_UINT32 *dataAddr = (A_UINT32 *)usbDesc->dataAddr;
A_UINT32 data;
if ( ( usbDesc->dataSize & 3 ) != 0 ) {
len += 1;
}
for ( i = 0; i < len; i++ ) {
data = dataAddr[i];
dataAddr[i] = __bswap32(data);
}
}
void
ar5416Set11nRateScenario(struct ath_hal *ah, void *ds,
void *lastds,
u_int dur_update_en, u_int rts_cts_rate, u_int rts_cts_duration,
HAL_11N_RATE_SERIES series[], u_int nseries,
u_int flags, u_int32_t smartAntenna)
#endif
{
struct ath_hal_private *ap = AH_PRIVATE(ah);
struct ar5416_desc *ads = AR5416DESC(ds);
struct ar5416_desc *last_ads = AR5416DESC(lastds);
u_int32_t ds_ctl0;
u_int mode;
HALASSERT(nseries == 4);
(void)nseries;
(void)rts_cts_duration; /* use H/W to calculate RTSCTSDuration */
/*
* Rate control settings override
*/
ds_ctl0 = ads->ds_ctl0;
if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
if (flags & HAL_TXDESC_RTSENA) {
ds_ctl0 &= ~AR_CTSEnable;
ds_ctl0 |= AR_RTSEnable;
} else {
ds_ctl0 &= ~AR_RTSEnable;
ds_ctl0 |= AR_CTSEnable;
}
} else {
ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
}
mode = ath_hal_get_curmode(ah, ap->ah_curchan);
if (ap->ah_config.ath_hal_desc_tpc) {
int16_t txpower;
txpower = ar5416GetRateTxPower(ah, mode, series[0].rate_index,
series[0].ch_sel);
if(series[0].tx_power_cap == 0)
{
/*For short range mode, set txpower to MAX to put series[0].TxPowerCap into the descriptor*/
txpower = HAL_TXPOWER_MAX;
}
ds_ctl0 &= ~AR_XmitPower0;
if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
u_int count;
for (count=0; count < nseries; count++) {
series[count].tx_power_cap -= AR5416_PWR_TABLE_OFFSET_DB * 2;
}
}
ds_ctl0 |= set11nTxPower(0, AH_MIN(txpower, series[0].tx_power_cap));
}
ads->ds_ctl0 = ds_ctl0;
ads->ds_ctl2 = set11nTries(series, 0)
| set11nTries(series, 1)
| set11nTries(series, 2)
| set11nTries(series, 3)
| (dur_update_en ? AR_DurUpdateEna : 0)
| SM(0, AR_BurstDur);
ads->ds_ctl3 = set11nRate(series, 0)
| set11nRate(series, 1)
| set11nRate(series, 2)
| set11nRate(series, 3);
ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
| set11nPktDurRTSCTS(series, 1);
ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
| set11nPktDurRTSCTS(series, 3);
ads->ds_ctl7 = set11nRateFlags(series, 0)
| set11nRateFlags(series, 1)
| set11nRateFlags(series, 2)
| set11nRateFlags(series, 3)
| SM(rts_cts_rate, AR_RTSCTSRate);
if (ap->ah_config.ath_hal_desc_tpc && AR_SREV_OWL_20_OR_LATER(ah)) {
int16_t txpower;
txpower = ar5416GetRateTxPower(
ah, mode, series[1].rate_index, series[1].ch_sel);
ads->ds_ctl9 =
set11nTxPower(1, AH_MIN(txpower, series[1].tx_power_cap));
txpower = ar5416GetRateTxPower(
ah, mode, series[2].rate_index, series[2].ch_sel);
ads->ds_ctl10 =
set11nTxPower(2, AH_MIN(txpower, series[2].tx_power_cap));
txpower = ar5416GetRateTxPower(
ah, mode, series[3].rate_index, series[3].ch_sel);
ads->ds_ctl11 =
set11nTxPower(3, AH_MIN(txpower, series[3].tx_power_cap));
}
#ifdef AH_NEED_DESC_SWAP
last_ads->ds_ctl2 = __bswap32(ads->ds_ctl2);
last_ads->ds_ctl3 = __bswap32(ads->ds_ctl3);
#else
last_ads->ds_ctl2 = ads->ds_ctl2;
last_ads->ds_ctl3 = ads->ds_ctl3;
#endif
}
/*
* Processing of HW TX descriptor.
*/
HAL_STATUS
ar5416ProcTxDesc(struct ath_hal *ah, void *desc)
{
struct ar5416_desc *ads = AR5416DESC(desc);
struct ath_desc *ds = (struct ath_desc *)desc;
struct ath_tx_status *ntxstat;
#ifdef AH_NEED_DESC_SWAP
if ((ads->ds_txstatus9 & __bswap32(AR_TxDone)) == 0)
return HAL_EINPROGRESS;
ar5416SwapTxDesc(ds);
#else
if ((ads->ds_txstatus9 & AR_TxDone) == 0)
return HAL_EINPROGRESS;
#endif
/*
* Use a local copy of ds/ads in the cacheable memory to
* improve the d-cache efficiency
*/
ntxstat = &(ds->ds_txstat);
/* Update software copies of the HW status */
ntxstat->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
ntxstat->ts_tstamp = ads->AR_SendTimestamp;
ntxstat->ts_status = 0;
ntxstat->ts_flags = 0;
if (ads->ds_txstatus1 & AR_ExcessiveRetries)
ntxstat->ts_status |= HAL_TXERR_XRETRY;
if (ads->ds_txstatus1 & AR_Filtered)
ntxstat->ts_status |= HAL_TXERR_FILT;
if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
ntxstat->ts_status |= HAL_TXERR_FIFO;
ar5416UpdateTxTrigLevel(ah, AH_TRUE);
}
if (ads->ds_txstatus9 & AR_TxOpExceeded)
ntxstat->ts_status |= HAL_TXERR_XTXOP;
if (ads->ds_txstatus1 & AR_TxTimerExpired)
ntxstat->ts_status |= HAL_TXERR_TIMER_EXPIRED;
if (ads->ds_txstatus1 & AR_DescCfgErr)
ntxstat->ts_flags |= HAL_TX_DESC_CFG_ERR;
if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
ntxstat->ts_flags |= HAL_TX_DATA_UNDERRUN;
ar5416UpdateTxTrigLevel(ah, AH_TRUE);
}
if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
ntxstat->ts_flags |= HAL_TX_DELIM_UNDERRUN;
ar5416UpdateTxTrigLevel(ah, AH_TRUE);
}
if (ads->ds_txstatus0 & AR_TxBaStatus) {
ntxstat->ts_flags |= HAL_TX_BA;
ntxstat->ba_low = ads->AR_BaBitmapLow;
ntxstat->ba_high = ads->AR_BaBitmapHigh;
}
ntxstat->tid = (ads->ds_txstatus9 & 0xf0000000) >>28;
/*
* Extract the transmit rate.
*/
ntxstat->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
switch (ntxstat->ts_rateindex) {
case 0:
ntxstat->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
break;
case 1:
ntxstat->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
break;
case 2:
ntxstat->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
break;
case 3:
ntxstat->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
break;
}
ntxstat->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
ntxstat->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
ntxstat->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
ntxstat->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
ntxstat->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
ntxstat->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
ntxstat->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
ntxstat->evm0 = ads->AR_TxEVM0;
ntxstat->evm1 = ads->AR_TxEVM1;
ntxstat->evm2 = ads->AR_TxEVM2;
ntxstat->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
ntxstat->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
ntxstat->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
ntxstat->ts_antenna = 0;
return HAL_OK;
}
