unsigned char DMA_SPI_Read(unsigned char* buf, unsigned long length, void (*fp)(void))
{
if (UCB1IFG & UCTXIFG)
{
DMA0IFG_CB = 0;
DMA1IFG_CB = fp;
// Setup DMA0
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) DummyBytesArray);
// Source block address
DMA0SZ = length; // Block size
//DMA0CTL = DMADT_2+DMASRCINCR_3+DMASBDB+DMALEVEL;
// Setup DMA1
__data16_write_addr((unsigned short) &DMA1DA,(unsigned long) buf);
// Destination single address
DMA1SZ = length; // Block size
//DMA1CTL = DMADT_2+DMADSTINCR_3+DMASBDB+DMALEVEL;
DMA0CTL &= (~DMAIFG);
DMA0CTL &= (~DMAIE);
DMA1CTL &= (~DMAIFG);
DMA1CTL |= DMAIE;
DMA0CTL |= DMAEN; // DMA0 Enable
DMA1CTL |= DMAEN; // DMA1 Enable
return 1;
}
return 0;
}
void main(void)
{
WDTCTL = WDT_ADLY_1000; // WDT 1000ms, ACLK, interval timer
SFRIE1 |= WDTIE; // Enable WDT interrupt
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP7 = PM_UCA0TXD; // Map UCA0TXD output to P2.7
PMAPPWD = 0; // Lock port mapping registers
P2DIR |= BIT7; // Set P2.7 as TX output
P2SEL |= BIT7; // Select P2.6 & P2.7 to UART function
UCA0CTL1 |= UCSWRST; // 8-bit characters
UCA0CTL1 = UCSSEL_1; // CLK = ACLK
UCA0BR0 = 0x03; // 32k/9600=3.41
UCA0BR1 = 0x00;
UCA0MCTL = UCBRS_3+UCBRF_0; // Modulation
UCA0CTL1 &= ~UCSWRST; // Release USCI state machine
DMACTL0 = DMA0TSEL_17; // USCI_A0 TXIFG trigger
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) String1);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCA0TXBUF);
// Destination single address
DMA0SZ = sizeof(String1); // Block size
DMA0CTL = DMASRCINCR_3+DMASBDB+DMALEVEL; // Repeat, inc src
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3 w/ interrupts
__no_operation(); // Required only for debugger
}
/**********************************************************************//**
* @brief Global API call to record audio on the mike.
*
* - Initializes the record using setupRecord()
* - Erases the memory reserved for audio recording
* - Records until the memory is full using record()
* - Shuts down the record using shutdownRecord()
*
* @param mode The mode of audio record
*
* - AUDIO_TEST_MODE ...for production test
* - AUDIO_DEMO_MODE ...called for user sample code
*
* @return none
*************************************************************************/
void audioRecord(unsigned char mode)
{
unsigned char i;
setupRecord();
halLcdPrintLine(" Erasing ", 6, INVERT_TEXT | OVERWRITE_TEXT);
halLcdPrintLineCol("----", 8, 12, OVERWRITE_TEXT);
// Not used in User Experience sample code
if (mode == AUDIO_TEST_MODE)
{
flashErase(MemstartTest, Memend);
__data16_write_addr((unsigned short)&DMA0DA, MemstartTest);
DMA0SZ = (long) (Memend - MemstartTest);
record();
if (DMA0SZ != ( long) (Memend - MemstartTest))
lastAudioByte = Memend - DMA0SZ;
else
lastAudioByte = Memend;
}
// Always used in User Experience sample code
else
{
flashEraseBank(AUDIO_MEM_START[0]);
flashEraseBank(AUDIO_MEM_START[1]);
flashEraseBank(AUDIO_MEM_START[2]);
flashErase(AUDIO_MEM_START[3], AUDIO_MEM_START[4]);
for (i=0;i<3;i++)
{
__data16_write_addr((unsigned short)&DMA0DA, AUDIO_MEM_START[i]);
DMA0SZ = AUDIO_MEM_START[i+1] - AUDIO_MEM_START[i] - 1;
record();
if (DMA0SZ != AUDIO_MEM_START[i+1] - AUDIO_MEM_START[i] - 1)
{
lastAudioByte = AUDIO_MEM_START[i+1] - DMA0SZ;
break;
}
else lastAudioByte = AUDIO_MEM_START[i+1]-1;
}
}
shutdownRecord();
}
/**********************************************************************//**
* @brief Initializes the microphone, ADC, and DMA for recording.
*
* @param none
*
* @return none
*************************************************************************/
static void setupRecord(void)
{
LED_PORT_OUT |= LED_1; // Turn on LED
AUDIO_PORT_OUT |= MIC_POWER_PIN;
AUDIO_PORT_OUT &= ~MIC_INPUT_PIN;
AUDIO_PORT_SEL |= MIC_INPUT_PIN;
lcdBackLightLevelSettingLOCAL = halLcdGetBackLight();
if (lcdBackLightLevelSettingLOCAL < 5)
halLcdSetBackLight(0);
else
halLcdSetBackLight(16);
TBCTL = TBSSEL_2; // Use SMCLK as Timer_B source
TBR = 0;
TBCCR0 = 2047; // Initialize TBCCR0
TBCCR1= 2047- 100;
TBCCTL1 = OUTMOD_7;
UCSCTL8 |= MODOSCREQEN;
ADC12CTL2 = ADC12RES_0; // Select 8-bit resolution
ADC12CTL0 = ADC12ON + ADC12SHT02 ;
ADC12CTL1 = ADC12SHP + ADC12CONSEQ_2 + ADC12SSEL_2 + ADC12SHS_3;
//Sequence of channels, once
ADC12MCTL0 = MIC_INPUT_CHAN | ADC12EOS ; //VeREF+ and VeREF-
ADC12CTL0 |= ADC12ENC; //Enable
ADC12CTL0 |= ADC12SC; //Start conversion
DMACTL0 = DMA0TSEL_24; // ADC12IFGx triggers DMA0
__data16_write_addr((unsigned short)&DMA0SA, ADC12MEM0_);// Src address = ADC12 module
halButtonsInterruptDisable( BUTTON_S1 );
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog
//.......................
P5SEL |= BIT4+BIT5; // Select XT1
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
UCSCTL3 = 0; // FLL Reference Clock = XT1
// Loop until XT1,XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive strength
UCSCTL4 |= SELA_0 + SELS_4 + SELM_4; // ACLK = LFTX1
// SMCLK = default DCO
// MCLK = default DCO
//................
P4SEL = BIT4+BIT5; // P4.4,5 = UART1 TXD/RXD
// configure USCI_A1 UART
UCA1CTL1 = UCSSEL_1; // ACLK
UCA1BR0 = 0x03; // 32768Hz 9600 32k/9600=3.41
UCA1BR1 = 0x0;
UCA1MCTL = UCBRS_3+UCBRF_0; // Modulation UCBRSx = 3
UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
// configure DMA0
DMACTL0 = DMA0TSEL_1; // 0-CCR2IFG
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) String1);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCA1TXBUF);
// Destination single address
DMA0SZ = sizeof String1-1; // Block size
DMA0CTL = DMADT_4 + DMASRCINCR_3 + DMASBDB + DMAEN;// Rpt, inc src, enable
TA0CCR0 = 8192; // Char freq = TACLK/CCR0
TA0CCR2 = 1; // For DMA0 trigger
TA0CTL = TASSEL_1 + MC_1; // ACLK, up-mode
_BIS_SR(LPM3_bits); // Enter LPM3
}
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
P1DIR |= 0x01; // P1.0 output
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) 0x1C00);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) 0x1C20);
// Destination single address
DMA0SZ = 16; // Block size
DMA0CTL = DMADT_5+DMASRCINCR_3+DMADSTINCR_3; // Rpt, inc
DMA0CTL |= DMAEN; // Enable DMA0
while(1)
{
P1OUT |= 0x01; // P1.0 = 1, LED on
DMA0CTL |= DMAREQ; // Trigger block transfer
P1OUT &= ~0x01; // P1.0 = 0, LED off
}
}
void main(void)
{
WDTCTL = WDT_ADLY_1000; // WDT 1000ms, ACLK, interval timer
SFRIE1 |= WDTIE; // Enable WDT interrupt
P1OUT &= ~0x01; // Clear P1.0 LED
P1DIR |= BIT0;
P3SEL |= BIT3+BIT4; // P3.3,4 = USCI_A0 SPI Option
P2DIR |= BIT7; // P2.7 UCA0CLK
P2SEL |= BIT7;
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL0 = UCMST+UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCA0CTL1 = UCSSEL_2; // SMCLK
UCA0BR0 = 0x02; // /2
UCA0BR1 = 0x00; //
UCA0MCTL = 0x00; // No modulation
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
DMACTL0 = DMA1TSEL_16+DMA0TSEL_17; // DMA0 - UCA0TXIFG
// DMA1 - UCA0RXIFG
// Setup DMA0
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &TxString);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCA0TXBUF);
// Destination single address
DMA0SZ = 1; // Block size
DMA0CTL = DMASRCINCR_3+DMASBDB+DMALEVEL; // inc src
// Setup DMA1
__data16_write_addr((unsigned short) &DMA1SA,(unsigned long) &UCA0RXBUF);
// Source block address
__data16_write_addr((unsigned short) &DMA1DA,(unsigned long) &RxString);
// Destination single address
DMA1SZ = 1; // Block size
DMA1CTL = DMADSTINCR_3+DMASBDB+DMALEVEL; // inc dst
TxString = RxString = 0; // Clear TxString
// Clear RxString
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3 w/ interrupts
__no_operation(); // Required only for debugger
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
// Configure ADC10;
ADC10CTL0 = ADC10SHT_3 + ADC10MSC + ADC10ON;// 32ADCclks, ADC on
ADC10CTL1 = ADC10SHP + ADC10CONSEQ_2 + ADC10SSEL_3 + ADC10DIV_1; // SMCLK/2
// Sampling timer, rpt single ch
ADC10CTL2 = ADC10RES; // 10-bit resolution
ADC10MCTL0 = ADC10INCH_11 + ADC10SREF_1; // Vref+, A10
// Configure internal reference
while(REFCTL0 & REFGENBUSY); // If ref generator busy, WAIT
REFCTL0 |= REFVSEL_0+REFON; // Select internal ref = 1.5V
// Internal Reference ON
__delay_cycles(75); // Delay (~75us) for Ref to settle
// Configure DMA (ADC10IFG trigger)
DMACTL0 = DMA0TSEL_24; // ADC10IFG trigger
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &ADC10MEM0);
// Source single address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) 0x1800);
// Destination array address
DMA0SZ = 0x20; // 32 conversions
DMA0CTL = DMADT_4 + DMADSTINCR_3 + DMAEN + DMAIE; // Rpt, inc dest, word access,
// enable int after 32 conversions
while(1)
{
FCTL3 = FWKEY; // Lock = 0
FCTL1 = FWKEY + ERASE; // Erase bit = 1
*(unsigned int *)0x1800 = 0; // Dummy write to erase Flash seg
while (ADC10CTL1 & BUSY); // Wait if ADC10 core is active
FCTL1 = FWKEY + WRT; // Write bit = 1
ADC10CTL0 |= ADC10ENC + ADC10SC; // Start sampling
__bis_SR_register(CPUOFF + GIE); // LPM0, ADC10_ISR will force exit
FCTL3 = FWKEY + LOCK; // Lock = 1
__no_operation(); // << SET BREAKPOINT HERE
__delay_cycles(5000); // Delay between conversions
}
}
void main(void)
{
WDTCTL = WDT_ADLY_1000; // WDT 1000ms, ACLK, interval timer
SFRIE1 |= WDTIE; // Enable WDT interrupt
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP6 = PM_UCA0RXD; // Map UCA0RXD output to P2.6
P2MAP7 = PM_UCA0TXD; // Map UCA0TXD output to P2.7
PMAPPWD = 0; // Lock port mapping registers
P2DIR |= BIT7; // Set P2.7 as TX output
P2SEL |= BIT6 + BIT7; // Select P2.6 & P2.7 to UART function
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 9; // 1MHz 115200 (see User's Guide)
UCA0BR1 = 0; // 1MHz 115200
UCA0MCTL |= UCBRS_1 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx=0
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
DMACTL0 = DMA1TSEL_16+DMA0TSEL_17; // DMA0 - UCA0TXIFG
// DMA1 - UCA0RXIFG
// Setup DMA0
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &TxString);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCA0TXBUF);
// Destination single address
DMA0SZ = 1; // Block size
DMA0CTL = DMASRCINCR_0+DMASBDB+DMALEVEL; // src does not change
// Setup DMA1
__data16_write_addr((unsigned short) &DMA1SA,(unsigned long) &UCA0RXBUF);
// Source block address
__data16_write_addr((unsigned short) &DMA1DA,(unsigned long) &RxString);
// Destination single address
DMA1SZ = 1; // Block size
DMA1CTL = DMADSTINCR_0+DMASBDB+DMALEVEL+DMADT_4+DMAEN; // dst does not change
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Hold WDT
P1OUT &= ~BIT0; // P1.0 clear
P1DIR |= BIT0; // P1.0 output
P5SEL |= BIT7; // P5.7/TB1 option select
P5DIR |= BIT7; // Output direction
P6SEL |= BIT0; // Enable A/D channel A0
//Setup Timer B0
TBCCR0 = 0xFFFE;
TBCCR1 = 0x8000;
TBCCTL1 = OUTMOD_3; // CCR1 set/reset mode
TBCTL = TBSSEL_2+MC_1+TBCLR; // SMCLK, Up-Mode
// Setup ADC12
ADC12CTL0 = ADC12SHT0_15+ADC12MSC+ADC12ON;// Sampling time, MSC, ADC12 on
ADC12CTL1 = ADC12SHS_3+ADC12CONSEQ_2; // Use sampling timer; ADC12MEM0
// Sample-and-hold source = CCI0B =
// TBCCR1 output
// Repeated-single-channel
ADC12MCTL0 = ADC12SREF_0+ADC12INCH_0; // V+=AVcc V-=AVss, A0 channel
ADC12CTL0 |= ADC12ENC;
// Setup DMA0
DMACTL0 = DMA0TSEL_24; // ADC12IFGx triggered
DMACTL4 = DMARMWDIS; // Read-modify-write disable
DMA0CTL &= ~DMAIFG;
DMA0CTL = DMADT_4+DMAEN+DMADSTINCR_3+DMAIE; // Rpt single tranfer, inc dst, Int
DMA0SZ = 1; // DMA0 size = 1
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &ADC12MEM0);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &DMA_DST);
// Destination single address
__bis_SR_register(LPM0_bits + GIE); // LPM0 w/ interrupts
__no_operation(); // used for debugging
}
void main(void)
{
WDTCTL = WDT_ADLY_1000; // WDT 1000ms, ACLK, interval timer
SFRIE1 |= WDTIE; // Enable WDT interrupt
P3SEL |= 0x30; // P3.4,5 = USCI_A0 TXD/RXD
UCA0CTL1 |= UCSWRST; // 8-bit characters
UCA0CTL1 = UCSSEL_1; // CLK = ACLK
UCA0BR0 = 0x03; // 32k/9600=3.41
UCA0BR1 = 0x00;
UCA0MCTL = UCBRS_3+UCBRF_0; // Modulation
UCA0CTL1 &= ~UCSWRST; // Release USCI state machine
DMACTL0 = DMA0TSEL_17; // USCI_A0 TXIFG trigger
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) String1);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCA0TXBUF);
// Destination single address
DMA0SZ = sizeof(String1); // Block size
DMA0CTL = DMASRCINCR_3+DMASBDB+DMALEVEL; // Repeat, inc src
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3 w/ interrupts
__no_operation(); // Required only for debugger
}
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
P1DIR |= 0x01; // P1.0 output
/* Initialize DMA */
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) 0x1C00);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) 0x1C20);
// Destination single address
DMA0SZ = 16; // Block size
DMA0CTL = DMADT_5+DMASRCINCR_3+DMADSTINCR_3; // Rpt, inc
DMA0CTL |= DMAEN; // Enable DMA0
while(1)
{
P1OUT |= 0x01; // P1.0 = 1, LED on
DMA0CTL |= DMAREQ; // Trigger block transfer
__delay_cycles(64); // Provide sufficient time for DMA xfer
__no_operation(); // Set breakpoint here
P1OUT &= ~0x01; // P1.0 = 0, LED off
}
}
//*****************************************************************************
//
//! Sets source address and the direction that the source address will move
//! after a transfer.
//!
//! \param baseAddress is the base address of the DMA module.
//! \param channelSelect is the specified channel to set source address
//! direction for.
//! Valid values are
//! \b DMA_CHANNEL_0
//! \b DMA_CHANNEL_1
//! \b DMA_CHANNEL_2
//! \b DMA_CHANNEL_3
//! \b DMA_CHANNEL_4
//! \b DMA_CHANNEL_5
//! \b DMA_CHANNEL_6
//! \b DMA_CHANNEL_7
//! \param srcAddress is the address of where the data will be transfered from.
//! Modified bits are \b DMAxSA of \b DMAxSA register.
//! \param directionSelect is the specified direction of the source address
//! after a transfer.
//! Valid values are
//! \b DMA_DIRECTION_UNCHANGED
//! \b DMA_DIRECTION_DECREMENT
//! \b DMA_DIRECTION_INCREMENT
//! Modified bits are \b DMASRCINCR of \b DMAxCTL register.
//!
//! This function sets the source address and the direction that the source
//! address will move after a transfer is complete. It may be incremented,
//! decremented, or unchanged.
//!
//! \return NONE
//
//*****************************************************************************
void DMA_setSrcAddress (unsigned int baseAddress,
unsigned char channelSelect,
unsigned long srcAddress,
unsigned int directionSelect)
{
ASSERT(channelSelect <= DMA_CHANNEL_7);
ASSERT(directionSelect <= DMA_DIRECTION_INCREMENT);
//Set the Source Address
__data16_write_addr((unsigned short)(baseAddress + channelSelect + DMA0SA_O),
srcAddress);
//Reset bits before setting them
HWREG(baseAddress + channelSelect + OFS_DMA0CTL) &= ~(DMASRCINCR_3);
HWREG(baseAddress + channelSelect + OFS_DMA0CTL) |= directionSelect;
}
//*****************************************************************************
//
//! Sets the destination address and the direction that the destination address
//! will move after a transfer.
//!
//! \param baseAddress is the base address of the DMA module.
//! \param channelSelect is the specified channel to set the destination address
//! direction for.
//! Valid values are
//! \b DMA_CHANNEL_0
//! \b DMA_CHANNEL_1
//! \b DMA_CHANNEL_2
//! \b DMA_CHANNEL_3
//! \b DMA_CHANNEL_4
//! \b DMA_CHANNEL_5
//! \b DMA_CHANNEL_6
//! \b DMA_CHANNEL_7
//! \param dstAddress is the address of where the data will be transfered to.
//! Modified bits are \b DMAxDA of \b DMAxDA register.
//! \param directionSelect is the specified direction of the destination address
//! after a transfer.
//! Valid values are
//! \b DMA_DIRECTION_UNCHANGED
//! \b DMA_DIRECTION_DECREMENT
//! \b DMA_DIRECTION_INCREMENT
//! Modified bits are \b DMADSTINCR of \b DMAxCTL register.
//!
//! This function sets the destination address and the direction that the
//! destination address will move after a transfer is complete. It may be
//! incremented, decremented, or unchanged.
//!
//! \return NONE
//
//*****************************************************************************
void DMA_setDstAddress (unsigned int baseAddress,
unsigned char channelSelect,
unsigned long dstAddress,
unsigned int directionSelect)
{
ASSERT(channelSelect <= DMA_CHANNEL_7);
ASSERT(directionSelect <= DMA_DIRECTION_INCREMENT);
//Set the Destination Address
__data16_write_addr((unsigned short)(baseAddress + channelSelect + DMA0DA_O),
dstAddress);
//Reset bits before setting them
HWREG(baseAddress + channelSelect + OFS_DMA0CTL) &= ~(DMADSTINCR_3);
HWREG(baseAddress + channelSelect + OFS_DMA0CTL) |= (directionSelect << 2);
}
__interrupt void DMA_ISR(void)
{
switch(__even_in_range(DMAIV,16))
{
case 0: break;
case 2: // DMA0IFG = DMA Channel 0
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long)(pDST += 3));
if(pDST - DMA_DST == 24)
pDST = DMA_DST;
break;
case 4: break; // DMA1IFG = DMA Channel 1
case 6: break; // DMA2IFG = DMA Channel 2
case 8: break; // DMA3IFG = DMA Channel 3
case 10: break; // DMA4IFG = DMA Channel 4
case 12: break; // DMA5IFG = DMA Channel 5
case 14: break; // DMA6IFG = DMA Channel 6
case 16: break; // DMA7IFG = DMA Channel 7
default: break;
}
}
unsigned char DMA_SPI_Write(unsigned char* buf, unsigned long length, void (*fp)(void))
{
if (UCB1IFG & UCTXIFG)
{
DMA0IFG_CB = fp;
DMA1IFG_CB = 0;
// Setup DMA0
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) buf);
// Source block address
DMA0SZ = length;
//DMA0CTL = DMADT_2+DMASRCINCR_3+DMASBDB+DMALEVEL;
DMA0CTL &= (~DMAIFG);
DMA0CTL |= DMAIE;
DMA1CTL &= (~DMAIFG);
DMA1CTL &= (~DMAIE); // disale DMA1 interrupt
DMA0CTL |= DMAEN; // DMA0 Enable
return 1;
}
return 0;
}
void DMAInit(void)
{
DMACTL0 = DMA0TSEL_24+DMA1TSEL_24; // DMA0 1 - ADC12IFGx
DMACTL1 = DMA2TSEL_24; //DMA3TSEL_24; // DMA2
DMACTL4 = DMARMWDIS; // Read-modify-write disable
// Setup DMA0
__data16_write_addr((unsigned short) &DMA0SA,(uint32) &ADC12MEM0);
// __data16_write_addr((unsigned short) &DMA0SA,(unsigned short) &ADC12MEM0);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &DMA_A0);
// Destination single address
DMA0SZ = 1; // Block size
DMA0CTL &= ~DMAIFG;
DMA0CTL = DMADT_4+DMAEN+DMADSTINCR_0+DMAIE; // Rpt single tranfer, dst, Int
// Setup DMA1
__data16_write_addr((unsigned short) &DMA1SA,(unsigned long) &ADC12MEM1);
// Source block address
__data16_write_addr((unsigned short) &DMA1DA,(unsigned long) &DMA_A1);
// Destination single address
DMA1SZ = 1; // Block size
DMA1CTL &= ~DMAIFG;
DMA1CTL = DMADT_4+DMAEN+DMADSTINCR_0+DMAIE; // Rpt single tranfer, dst, Int
// Setup DMA2
__data16_write_addr((unsigned short) &DMA2SA,(unsigned long) &ADC12MEM2);
// Source block address
__data16_write_addr((unsigned short) &DMA2DA,(unsigned long) &DMA_A2);
// Destination single address
DMA2SZ = 1; // Block size
DMA2CTL &= ~DMAIFG;
DMA2CTL = DMADT_4+DMAEN+DMADSTINCR_0+DMAIE; // Rpt single tranfer, dst, Int
// // Setup DMA3
// __data16_write_addr((unsigned short) &DMA3SA,(unsigned long) &ADC12MEM3);
// // Source block address
// __data16_write_addr((unsigned short) &DMA3DA,(unsigned long) &DMA_A3);
// // Destination single address
// DMA3SZ = 1; // Block size
// DMA3CTL &= ~DMAIFG;
// DMA3CTL = DMADT_4+DMAEN+DMADSTINCR_0+DMAIE; // Rpt single tranfer, dst, Int
}
static void Write(unsigned char Cmd, unsigned char *pBuffer, unsigned int Size)
{
EnableSmClkUser(LCD_USER);
LCD_CS_ASSERT();
#if LCD_DMA
LcdDmaBusy = 1;
/* send the lcd write command before starting the dma */
LCD_SPI_UCBxTXBUF = Cmd;
while (!(LCD_SPI_UCBxIFG&UCTXIFG));
/* USCIB0 TXIFG is the DMA trigger
* DMACTL1 controls dma2 and [dma3]
*/
DMACTL1 = DMA2TSEL_19;
__data16_write_addr((unsigned short) &DMA2SA, (unsigned long) pBuffer);
__data16_write_addr((unsigned short) &DMA2DA, (unsigned long) &LCD_SPI_UCBxTXBUF);
DMA2SZ = Size;
/*
* single transfer, increment source address, source byte and dest byte,
* level sensitive, enable interrupt, clear interrupt flag
*/
DMA2CTL = DMADT_0 + DMASRCINCR_3 + DMASBDB + DMALEVEL + DMAIE;
/* start the transfer */
DMA2CTL |= DMAEN;
while(LcdDmaBusy);
#else
/* send the lcd write command */
LCD_SPI_UCBxTXBUF = Cmd;
while (!(LCD_SPI_UCBxIFG&UCTXIFG));
for (unsigned int i = 0; i < Size; ++i)
{
LCD_SPI_UCBxTXBUF = pBuffer[i];
while (!(LCD_SPI_UCBxIFG&UCTXIFG));
}
#endif
/* add one more dummy byte at the end */
LCD_SPI_UCBxTXBUF = 0x00;
while (!(LCD_SPI_UCBxIFG&UCTXIFG));
/* wait for shift to complete ( ~3 us ) */
while((LCD_SPI_UCBxSTAT & 0x01) != 0);
LCD_SPI_UCBxTXBUF = LCD_STATIC_CMD;
while (!(LCD_SPI_UCBxIFG&UCTXIFG));
LCD_SPI_UCBxTXBUF = 0x00;
while (!(LCD_SPI_UCBxIFG&UCTXIFG));
/* now the chip select can be deasserted */
LCD_CS_DEASSERT();
DisableSmClkUser(LCD_USER);
}
void init_DMA_SPI(unsigned char db)
{
if (!DMA_SPI_enabled)
{
//unsigned short i;
//for (i = 0; i < 1024; ++i)
//{
// DummyBytesArray[i] = db;
//}
// CS config for SD CARD
P4SEL &= 0xFE;
P4DIR |= 0x01;
P4OUT |= 0x01;
// CS config for FRAM
P4SEL &= 0xFD;
P4DIR |= 0x02;
P4OUT |= 0x02;
// spi ucb1 config
P3SEL |= 0x80;
P5SEL |= 0x30;
UCB1CTL1 |= UCSWRST; // **Put state machine in reset**
UCB1CTL0 = UCMST+UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCB1CTL1 = UCSSEL_2; // SMCLK
UCB1BR0 = 0x02; // /2
UCB1BR1 = 0x00; //
//UCB1MCTL = 0x00; // No modulation
UCB1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
DMACTL0 = DMA0TSEL_23 + DMA1TSEL_22; // DMA0 - UCA0TXIFG
// DMA1 - UCA0RXIFG
// Setup DMA0
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCB1TXBUF);
// Destination single address
DMA0SZ = 0; // Block size
DMA0CTL = DMASRCINCR_3+DMASBDB+DMALEVEL; // inc src
// Setup DMA1
__data16_write_addr((unsigned short) &DMA1SA,(unsigned long) &UCB1RXBUF);
// Source block address
DMA1SZ = 0; // Block size
DMA1CTL = DMADSTINCR_3+DMASBDB+DMALEVEL; // inc dst
__bis_SR_register(/*LPM3_bits + */GIE); // Enter LPM3 w/ interrupts
__no_operation(); // Required only for debugger
DMA0CTL |= DMADT_2;
DMA1CTL |= DMADT_2;
// DMA interrupt for channer 1 and 2
DMA0CTL &= (~DMAIFG);
DMA0CTL += DMAIE;
DMA1CTL &= (~DMAIFG);
DMA1CTL += DMAIE;
DMA_SPI_enabled = 1;
}
}
