bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config)
{
uint_fast8_t positiveTerminalInput = __getRegisterSettingForInput(
config->positiveTerminalInput);
uint_fast8_t negativeTerminalInput = __getRegisterSettingForInput(
config->negativeTerminalInput);
bool retVal = true;
ASSERT(positiveTerminalInput < 0x10); ASSERT(negativeTerminalInput < 0x10);
ASSERT(positiveTerminalInput != negativeTerminalInput);
ASSERT(
config->outputFilterEnableAndDelayLevel
<= COMP_E_FILTEROUTPUT_DLYLVL4);
/* Reset COMPE Control 1 & Interrupt Registers for initialization */
COMP_E_CMSIS(comparator)->CTL0 = 0;
COMP_E_CMSIS(comparator)->INT = 0;
// Set the Positive Terminal
if (COMP_E_VREF != positiveTerminalInput)
{
// Enable Positive Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IPEN
+ positiveTerminalInput;
// Disable the input buffer
COMP_E_CMSIS(comparator)->CTL3 |= (1 << positiveTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2,COMP_E_CTL2_RSEL_OFS) = 0;
}
// Set the Negative Terminal
if (COMP_E_VREF != negativeTerminalInput)
{
// Enable Negative Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IMEN
+ (negativeTerminalInput << 8);
// Disable the input buffer
COMP_E_CMSIS(comparator)->CTL3 |= (1 << negativeTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_RSEL_OFS) = 1;
}
// Reset and Set COMPE Control 1 Register
COMP_E_CMSIS(comparator)->CTL1 = config->powerMode
+ config->outputFilterEnableAndDelayLevel
+ config->invertedOutputPolarity;
return retVal;
}
bool Comp_E_init(uint16_t baseAddress,
Comp_E_initParam *param)
{
uint8_t positiveTerminalInput = __getRegisterSettingForInput(
param->posTerminalInput);
uint8_t negativeTerminalInput = __getRegisterSettingForInput(
param->negTerminalInput);
bool retVal = STATUS_SUCCESS;
//Reset COMPE Control 1 & Interrupt Registers for initialization (OFS_CECTL3
//is not reset because it controls the input buffers of the analog signals
//and may cause parasitic effects if an analog signal is still attached and
//the buffer is re-enabled
HWREG16(baseAddress + OFS_CECTL0) &= 0x0000;
HWREG16(baseAddress + OFS_CEINT) &= 0x0000;
//Set the Positive Terminal
if(COMP_E_VREF != positiveTerminalInput)
{
//Enable Positive Terminal Input Mux and Set it to the appropriate input
HWREG16(baseAddress + OFS_CECTL0) |= CEIPEN + positiveTerminalInput;
//Disable the input buffer
HWREG16(baseAddress + OFS_CECTL3) |= (1 << positiveTerminalInput);
}
else
{
//Reset and Set COMPE Control 2 Register
HWREG16(baseAddress + OFS_CECTL2) &= ~(CERSEL); //Set Vref to go to (+)terminal
}
//Set the Negative Terminal
if(COMP_E_VREF != negativeTerminalInput)
{
//Enable Negative Terminal Input Mux and Set it to the appropriate input
HWREG16(baseAddress +
OFS_CECTL0) |= CEIMEN + (negativeTerminalInput << 8);
//Disable the input buffer
HWREG16(baseAddress + OFS_CECTL3) |= (1 << negativeTerminalInput);
}
else
{
//Reset and Set COMPE Control 2 Register
HWREG16(baseAddress + OFS_CECTL2) |= CERSEL; //Set Vref to go to (-) terminal
}
//Reset and Set COMPE Control 1 Register
HWREG16(baseAddress + OFS_CECTL1) =
+param->outputFilterEnableAndDelayLevel //Set the filter enable bit and delay
+ param->invertedOutputPolarity; //Set the polarity of the output
return (retVal);
}
