static void __gptimer_set_mode(enum clock_event_mode mode, struct clock_event_device *c) { unsigned int saved; switch (mode) { case CLOCK_EVT_MODE_PERIODIC: __gptimer_ctl(EVENT_TIMER, TIMER_DISABLE, PERIOD_MODE); __raw_writel(LATCH, TIMER_LOAD(EVENT_TIMER)); __gptimer_ctl(EVENT_TIMER, TIMER_ENABLE, PERIOD_MODE); __raw_writel(TIMER_INT_EN, TIMER_INT(EVENT_TIMER)); break; case CLOCK_EVT_MODE_ONESHOT: __gptimer_ctl(EVENT_TIMER, TIMER_ENABLE, ONETIME_MODE); __raw_writel(TIMER_INT_EN, TIMER_INT(EVENT_TIMER)); break; case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_UNUSED: saved = __raw_readl(TIMER_CTL(EVENT_TIMER)) & PERIOD_MODE; __gptimer_ctl(EVENT_TIMER, TIMER_DISABLE, saved); break; case CLOCK_EVT_MODE_RESUME: saved = __raw_readl(TIMER_CTL(EVENT_TIMER)) & PERIOD_MODE; __gptimer_ctl(EVENT_TIMER, TIMER_ENABLE, saved); break; } }
static int __bctimer_set_next_event(unsigned long cycles, struct clock_event_device *c) { while (TIMER_INT_BUSY & __raw_readl(TIMER_INT(BC_CPU, BC_TIMER))) ; __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_DISABLE, ONETIME_MODE); __raw_writel(cycles, TIMER_LOAD(BC_CPU, BC_TIMER)); __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, ONETIME_MODE); return 0; }
static int __gptimer_set_next_event(unsigned long cycles, struct clock_event_device *c) { __gptimer_ctl(EVENT_TIMER, TIMER_DISABLE, ONETIME_MODE); __raw_writel(cycles, TIMER_LOAD(EVENT_TIMER)); __gptimer_ctl(EVENT_TIMER, TIMER_ENABLE, ONETIME_MODE); return 0; }
static int __gptimer_set_next_event(unsigned long cycles, struct clock_event_device *c) { int cpu = smp_processor_id(); while (TIMER_INT_BUSY & __raw_readl(TIMER_INT(cpu, EVENT_TIMER))) ; __gptimer_ctl(cpu, EVENT_TIMER, TIMER_DISABLE, ONETIME_MODE); __raw_writel(cycles, TIMER_LOAD(cpu, EVENT_TIMER)); __gptimer_ctl(cpu, EVENT_TIMER, TIMER_ENABLE, ONETIME_MODE); return 0; }
/* ****************************************************************** */ static void __gptimer_clocksource_init(const char *name, unsigned long hz) { /* disalbe irq since it's just a read source */ __raw_writel(0, TIMER_INT(SOURCE_TIMER)); __gptimer_ctl(SOURCE_TIMER, TIMER_DISABLE, PERIOD_MODE); __raw_writel(ULONG_MAX, TIMER_LOAD(SOURCE_TIMER)); __gptimer_ctl(SOURCE_TIMER, TIMER_ENABLE, PERIOD_MODE); clocksource_mmio_init(TIMER_VALUE(SOURCE_TIMER), name, hz, 300, 32, clocksource_mmio_readl_down); }
/* ****************************************************************** */ void __gptimer_clocksource_resume(struct clocksource *cs) { __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_ENABLE | TIMER_NEW, PERIOD_MODE); pr_debug("%s: timer_val=0x%x\n", __FUNCTION__, __raw_readl(TIMER_CNT_RD(e_cpu, SOURCE_TIMER))); }
static void __gptimer_clocksource_init(void) { /* disalbe irq since it's just a read source */ __raw_writel(0, TIMER_INT(e_cpu, SOURCE_TIMER)); __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_DISABLE | TIMER_NEW, PERIOD_MODE); __raw_writel(ULONG_MAX, TIMER_LOAD(e_cpu, SOURCE_TIMER)); __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_NEW, PERIOD_MODE); __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_ENABLE | TIMER_NEW, PERIOD_MODE); if (clocksource_register_hz (&clocksource_sprd, gptimer_clock_source_freq)) printk("%s: can't register clocksource\n", clocksource_sprd.name); }
void __init sci_enable_timer_early(void) { /* enable timer & syscnt in global regs */ int i = 0, j = 0; sci_glb_set(REG_AON_APB_APB_EB0, BIT_AON_TMR_EB | BIT_AP_SYST_EB | BIT_AP_TMR0_EB); #if defined CONFIG_LOCAL_TIMERS && !defined CONFIG_HAVE_ARM_ARCH_TIMER sci_glb_set(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB); for (i = 0; i < 4; i++) { #else sci_glb_clr(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB); for (i = 0; i < 2; i++) { #endif for (j = 0; j < 3; j++) { __gptimer_ctl(i, j, TIMER_DISABLE, 0); __raw_writel(TIMER_INT_CLR, TIMER_INT(i, j)); } } #if defined(CONFIG_ARCH_SCX30G) || defined(CONFIG_ARCH_SCX35L) /*timer1 fixed 32768 clk */ sched_clock_source_freq = 32768; #else /*timer2 clk source is from apb clk */ val = sci_glb_read(REG_AON_CLK_AON_APB_CFG, -1) & 0x3; if (val == 0x1) sched_clock_source_freq = 76800000; else if (val == 0x2) sched_clock_source_freq = 96000000; else if (val == 0x3) sched_clock_source_freq = 128000000; else sched_clock_source_freq = 26000000; /*default setting */ #endif gptimer_clock_source_freq = sched_clock_source_freq; #if !defined (CONFIG_HAVE_ARM_ARCH_TIMER) __sched_clock_init(sched_clock_source_freq); #endif } u32 get_sys_cnt(void) { u32 val = 0; val = __raw_readl(SYSCNT_SHADOW_CNT); return val; }