void __init u8500_map_io(void)
{
/*
* Map the UARTs early so that the DEBUG_LL stuff continues to work.
*/
iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
ux500_map_io();
iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
if (cpu_is_ux540_family())
iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
else
iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
_PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
}
static int __init ux500_rtcrtt_init(void)
{
if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
rtc_base = __io_address(U8500_RTC_BASE);
} else {
pr_err("timer-rtt: Unknown DB Asic!\n");
return -EINVAL;
}
if (request_irq(IRQ_DB8500_RTC, rtcrtt_interrupt,
IRQF_SHARED | IRQF_NO_SUSPEND,
"rtc-pl031-timer", rtc_base)) {
pr_err("rtc-rtt: failed to register irq\n");
}
ux500_rtcrtt_measure_latency(false);
return 0;
}
static void armctrl_unmask_irq(struct irq_data *d)
{
static const unsigned int enables[4] = {
ARM_IRQ_ENBL1,
ARM_IRQ_ENBL2,
ARM_IRQ_ENBL3,
0
};
if (d->irq >= FIQ_START) {
unsigned int data =
(unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
writel(0x80 | data, __io_address(ARM_IRQ_FAST));
} else {
unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
}
}
static void __init db8500_add_gpios(struct device *parent)
{
struct nmk_gpio_platform_data pdata = {
.supports_sleepmode = true,
};
dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
IRQ_DB8500_GPIO0, &pdata);
dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
}
static int usb_db8500_rx_dma_cfg[] = {
DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
DB8500_DMA_DEV39_USB_OTG_IEP_8
};
static int usb_db8500_tx_dma_cfg[] = {
DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
DB8500_DMA_DEV39_USB_OTG_OEP_8
};
static const char *db8500_read_soc_id(void)
{
void __iomem *uid = __io_address(U8500_BB_UID_BASE);
/* Throw these device-specific numbers into the entropy pool */
add_device_randomness(uid, 0x14);
return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
readl((u32 *)uid+1),
readl((u32 *)uid+1), readl((u32 *)uid+2),
readl((u32 *)uid+3), readl((u32 *)uid+4));
}
static void __init gic_init_irq(void)
{
#ifdef CONFIG_REALVIEW_MPCORE
unsigned int pldctrl;
writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + 0xd8);
pldctrl |= 0x00800000; /* New irq mode */
writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
#endif
gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
}
static ssize_t ux500_get_soc_id(char *buf, struct sysfs_soc_info *si)
{
void __iomem *uid_base;
int i;
ssize_t sz = 0;
if (dbx500_id.partnumber == 0x85) {
uid_base = __io_address(U8500_BB_UID_BASE);
for (i = 0; i < U8500_BB_UID_LENGTH; i++)
sz += sprintf(buf + sz, "%08x",
readl(uid_base + i * sizeof(u32)));
sz += sprintf(buf + sz, "\n");
} else {
/* Don't know where it is located for U5500 */
sz = sprintf(buf, "N/A\n");
}
return sz;
}
static void __init gic_init_irq(void)
{
unsigned int pldctrl;
/* new irq mode with no DCC */
writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
pldctrl |= 2 << 22;
writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
/* ARM11MPCore test chip GIC, primary */
gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
__io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
/* board GIC, secondary */
gic_init(1, IRQ_PB11MP_GIC_START,
__io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
__io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
}
void __init u8500_map_io(void)
{
/*
* Map the UARTs early so that the DEBUG_LL stuff continues to work.
*/
iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
ux500_map_io();
iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
if (cpu_is_u8500ed())
iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
else if (cpu_is_u8500v1())
iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
else if (cpu_is_u8500v2())
iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
_PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
}
void prcm_usb_reset(void)
{
unsigned int reg_value = 0;
void __iomem *rst_usb = __io_address(PRCM_RSTCTRL_USB);
reg_clr_bits(rst_usb, PRCM_RSTCTRL_USB_RST); //0
udelay(4);
reg_set_bits(rst_usb, PRCM_RSTCTRL_USB_RST); //1
udelay(800); //keep high to usb work normally
reg_value = PRCM_RSTCTRL_USB_RST_PORT0 | PRCM_RSTCTRL_USB_RST_PORT1 |
PRCM_RSTCTRL_USB_RST_PORT2 | PRCM_RSTCTRL_USB_RST_PORT3 ;
//port reset is level trigger and high trigger reset.
reg_set_bits(rst_usb, reg_value); //1
udelay(100);
reg_clr_bits(rst_usb, reg_value); //0
printk(KERN_NOTICE "usb reset...\n");
}
void ns2816_lcd_pixelclk_set(unsigned nr, unsigned int nf, unsigned int no)
{
unsigned int clkctrl;
void __iomem *ctrl_virt = __io_address(PRCM_LCD_CLKCTRL);
clkctrl = __raw_readl(ctrl_virt);
clkctrl &= ~(PRCM_LCD_CLKCTRL_FREQ_REFRESH);
clkctrl |= PRCM_LCD_CLKCTRL_CLK_EN;
__raw_writel(clkctrl, ctrl_virt);
clkctrl = __raw_readl(ctrl_virt);
clkctrl &= ~(PRCM_LCD_CLKCTRL_PLL_NR_MASK |
PRCM_LCD_CLKCTRL_PLL_NF_MASK |
PRCM_LCD_CLKCTRL_PLL_OD_MASK);
clkctrl |= ((nr -1) << 19) | ((nf - 1) << 6) | ((no - 1) << 2) | 3;
__raw_writel(clkctrl, ctrl_virt);
}
static int __init ux500_l2x0_unlock(void)
{
int i;
void __iomem *l2x0_base = __io_address(U8500_L2CC_BASE);
/*
* Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
* apparently locks both caches before jumping to the kernel. The
* l2x0 core will not touch the unlock registers if the l2x0 is
* already enabled, so we do it right here instead. The PL310 has
* 8 sets of registers, one per possible CPU.
*/
for (i = 0; i < 8; i++) {
writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
i * L2X0_LOCKDOWN_STRIDE);
writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
i * L2X0_LOCKDOWN_STRIDE);
}
return 0;
}
static void __init gic_init_irq(void)
{
if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE);
gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
29);
gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
} else {
gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE);
gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE),
IRQ_PBX_GIC_START);
gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE));
}
}
void __init versatile_init(void)
{
int i;
osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
platform_device_register(&versatile_flash_device);
platform_device_register(&versatile_i2c_device);
platform_device_register(&smc91x_device);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
#ifdef CONFIG_LEDS
leds_event = versatile_leds_event;
#endif
}
static inline void nusmart_i2s_playback(struct snd_pcm_substream *substream )
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
struct nusmart_runtime_data *rtd_prv = runtime->private_data;
void __iomem *scm_base = __io_address(0x051c0000);
unsigned int trans_size = readl(scm_base + SCM_DEMO_TRANS_SIZE);
// if(rtd_prv->interrupt_count % 16 == 0)
// DBG_PRINT("time8 interrupts, trans_size = %x\n", trans_size);
switch(rtd_prv->fmt) {
case SNDRV_PCM_FORMAT_S16_LE:
rtd_prv->tran_bytes_count = trans_size;
snd_pcm_period_elapsed(substream);
if(rtd_prv->tran_bytes_count == runtime->dma_bytes)
rtd_prv->tran_bytes_count = 0;
rtd_prv->interrupt_count++;
break;
}
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
static void __init bcm2708_timer_init(void)
{
/*
* Initialise to a known state (all timers off)
*/
writel(0, __io_address(ARM_T_CONTROL));
/*
* Make irqs happen for the system timer
*/
setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
timer0_clockevent.mult =
div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
timer0_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
timer0_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &timer0_clockevent);
timer0_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&timer0_clockevent);
}
static int __init LedBlinkModule_init(void)
{
int result;
s_pGpioRegisters =
(struct GpioRegisters *)__io_address(GPIO_BASE);
SetGPIOFunction(LedGpioPin, 0b001); //Output
setup_timer(&s_BlinkTimer, BlinkTimerHandler, 0);
result = mod_timer(&s_BlinkTimer,
jiffies + msecs_to_jiffies(s_BlinkPeriod));
BUG_ON(result < 0);
//create class & objects
s_pDeviceClass = class_create(THIS_MODULE, "LedBlink");
BUG_ON(IS_ERR(s_pDeviceClass));
s_pDeviceObject = device_create(s_pDeviceClass,
NULL, 0, NULL, "LEDBlink");
BUG_ON(IS_ERR(s_pDeviceObject));
result = device_create_file(s_pDeviceObject, &dev_attr_period);
BUG_ON(result < 0);
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
int i;
/*
* Initialise the present map, which describes the set of CPUs
* actually populated at the present time.
*/
for (i = 0; i < max_cpus; i++)
set_cpu_present(i, true);
scu_enable(scu_base_addr());
/*
* Write the address of secondary startup into the
* system-wide flags register. The BootMonitor waits
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
__raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
__io_address(REALVIEW_SYS_FLAGSSET));
}
/*
* Setup the local clock events for a CPU.
*/
void __cpuinit local_timer_setup(void)
{
unsigned int cpu = smp_processor_id();
struct clock_event_device *clk;
unsigned long flags;
void __iomem *int_reg;
u32 val, int_shift, irq;
if (cpu == 1) {
clk = &timer1_clockevent;
irq = tm_reg[TIMER_SYSTEM2].irq;
clk->cpumask = &cpumask_of_cpu(cpu);
clk->irq = irq;
clk->mult = div_sc(TIMER_CLOCK_TICK_RATE_PLL3,
NSEC_PER_SEC, clk->shift);
clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
clk->min_delta_ns = clockevent_delta2ns(0x7f, clk);
emxx_open_clockgate(tm_reg[TIMER_SYSTEM2].clkdev);
emxx_unreset_device(tm_reg[TIMER_SYSTEM2].rstdev);
local_irq_save(flags);
setup_irq(irq, &emxx_system_timer1_irq);
irq_desc[irq].cpu = cpu;
/* Setting interrupt */
int_reg = __io_address(EMXX_INTA_DIST_BASE) +
GIC_DIST_TARGET + (INT_TIMER1 & ~3);
int_shift = (irq % 4) * 8;
val = readl(int_reg) & ~(0xff << int_shift);
val |= 1 << (cpu + int_shift);
writel(val, int_reg);
local_irq_restore(flags);
clockevents_register_device(clk);
}
}
/* usb ref clk switch
* set switch clk
* reset usb
*/
void prcm_usb_sel_refclk(unsigned int refclk_sel, unsigned int refclk_div)
{
unsigned int reg_value = 0;
void __iomem *usb_refclk = __io_address(PRCM_RSTCTRL_USB_REFCLK);
reg_value = __raw_readl(usb_refclk);
if((refclk_sel == (reg_value & PRCM_RST_CTRL_USB_REFCLK_SEL_MASK) )
&& (refclk_div == (reg_value & PRCM_RST_CTRL_USB_REFCLK_DIV_MASK)))
{
printk(KERN_NOTICE "usb reference clock is already set to what your want! return.\n");
return;
}
reg_clr_bits(usb_refclk, PRCM_RST_CTRL_USB_REFCLK_SEL_MASK);
reg_set_bits(usb_refclk, refclk_sel);
reg_clr_bits(usb_refclk, PRCM_RST_CTRL_USB_REFCLK_DIV_MASK);
reg_set_bits(usb_refclk, refclk_div);
printk(KERN_NOTICE "alread set usb clock, refcle sel is %d, refclk divider is %d .\n"
, refclk_sel, refclk_div);
}
static struct clcd_panel *versatile_clcd_panel(void)
{
void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
struct clcd_panel *panel = &vga;
u32 val;
val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
if (val == SYS_CLCD_ID_SANYO_3_8)
panel = &sanyo_3_8_in;
else if (val == SYS_CLCD_ID_SANYO_2_5)
panel = &sanyo_2_5_in;
else if (val == SYS_CLCD_ID_EPSON_2_2)
panel = &epson_2_2_in;
else if (val == SYS_CLCD_ID_VGA)
panel = &vga;
else {
printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
val);
panel = &vga;
}
return panel;
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
pen_release = -1;
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static void __init realview_pb1176_init(void)
{
int i;
#ifdef CONFIG_CACHE_L2X0
/* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
#endif
clk_register(&realview_clcd_clk);
realview_flash_register(&realview_pb1176_flash_resource, 1);
platform_device_register(&realview_pb1176_smsc911x_device);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
#ifdef CONFIG_LEDS
leds_event = realview_leds_event;
#endif
}
static void __init realview_pbx_init(void)
{
int i;
#ifdef CONFIG_CACHE_L2X0
if (core_tile_pbxa9mp()) {
void __iomem *l2x0_base =
__io_address(REALVIEW_PBX_TILE_L220_BASE);
/* set RAM latencies to 1 cycle for eASIC */
writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
/* 16KB way size, 8-way associativity, parity disabled
* Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
l2x0_init(l2x0_base, 0x02520000, 0xc0000fff);
platform_device_register(&pmu_device);
}
#endif
realview_flash_register(realview_pbx_flash_resources,
ARRAY_SIZE(realview_pbx_flash_resources));
realview_eth_register(NULL, realview_pbx_smsc911x_resources);
platform_device_register(&realview_i2c_device);
platform_device_register(&realview_cf_device);
realview_usb_register(realview_pbx_isp1761_resources);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
#ifdef CONFIG_LEDS
leds_event = realview_leds_event;
#endif
realview_reset = realview_pbx_reset;
}
/*
* Detect which LCD panel is connected, and return the appropriate
* clcd_panel structure. Note: we do not have any information on
* the required timings for the 8.4in panel, so we presently assume
* VGA timings.
*/
static int realview_clcd_setup(struct clcd_fb *fb)
{
void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
const char *panel_name, *vga_panel_name;
unsigned long framesize;
u32 val;
if (machine_is_realview_eb()) {
/* VGA, 16bpp */
framesize = 640 * 480 * 2;
vga_panel_name = "VGA";
} else {
/* XVGA, 16bpp */
framesize = 1024 * 768 * 2;
vga_panel_name = "XVGA";
}
val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
if (val == SYS_CLCD_ID_SANYO_3_8)
panel_name = "Sanyo TM38QV67A02A";
else if (val == SYS_CLCD_ID_SANYO_2_5)
panel_name = "Sanyo QVGA Portrait";
else if (val == SYS_CLCD_ID_EPSON_2_2)
panel_name = "Epson L2F50113T00";
else if (val == SYS_CLCD_ID_VGA)
panel_name = vga_panel_name;
else {
pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
panel_name = vga_panel_name;
}
fb->panel = versatile_clcd_get_panel(panel_name);
if (!fb->panel)
return -EINVAL;
return versatile_clcd_setup_dma(fb, framesize);
}
/*
* integrator_clk_init() - set up the integrator clock tree
* @is_cp: pass true if it's the Integrator/CP else AP is assumed
*/
void __init integrator_clk_init(bool is_cp)
{
struct clk *clk;
/* APB clock dummy */
clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
clk_register_clkdev(clk, "apb_pclk", NULL);
/* UART reference clock */
clk = clk_register_fixed_rate(NULL, "uartclk", NULL, CLK_IS_ROOT,
14745600);
clk_register_clkdev(clk, NULL, "uart0");
clk_register_clkdev(clk, NULL, "uart1");
if (is_cp)
clk_register_clkdev(clk, NULL, "mmci");
/* 24 MHz clock */
clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
24000000);
clk_register_clkdev(clk, NULL, "kmi0");
clk_register_clkdev(clk, NULL, "kmi1");
if (!is_cp)
clk_register_clkdev(clk, NULL, "ap_timer");
if (!is_cp)
return;
/* 1 MHz clock */
clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT,
1000000);
clk_register_clkdev(clk, NULL, "sp804");
/* ICST VCO clock used on the Integrator/CP CLCD */
clk = icst_clk_register(NULL, &cp_icst_desc, "icst",
__io_address(INTEGRATOR_HDR_BASE));
clk_register_clkdev(clk, NULL, "clcd");
}
static void __init realview_eb_init(void)
{
int i;
#ifdef CONFIG_REALVIEW_MPCORE
/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
* Bits: .... ...0 0111 1001 0000 .... .... .... */
l2x0_init(__io_address(REALVIEW_MPCORE_L220_BASE), 0x00790000, 0xfe000fff);
#endif
clk_register(&realview_clcd_clk);
platform_device_register(&realview_flash_device);
platform_device_register(&realview_smc91x_device);
platform_device_register(&realview_i2c_device);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
#ifdef CONFIG_LEDS
leds_event = realview_leds_event;
#endif
}
static int __init ux500_l2x0_init(void)
{
u32 aux_val = 0x3e000000;
if (cpu_is_u8500_family() || cpu_is_ux540_family())
l2x0_base = __io_address(U8500_L2CC_BASE);
else
ux500_unknown_soc();
/* Unlock before init */
ux500_l2x0_unlock();
/* DBx540's L2 has 128KB way size */
if (cpu_is_ux540_family())
/* 128KB way size */
aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
else
/* 64KB way size */
aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
/* 64KB way size, 8 way associativity, force WA */
if (of_have_populated_dt())
l2x0_of_init(aux_val, 0xc0000fff);
else
l2x0_init(l2x0_base, aux_val, 0xc0000fff);
/*
* We can't disable l2 as we are in non secure mode, currently
* this seems be called only during kexec path. So let's
* override outer.disable with nasty assignment until we have
* some SMI service available.
*/
outer_cache.disable = NULL;
return 0;
}
static inline uint32_t timer_read(void)
{
/* STC: a free running counter that increments at the rate of 1MHz */
return readl(__io_address(ST_BASE + 0x04));
}
void __init bcm2708_init_irq(void)
{
armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
}
//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }