void set_backlight(uint32_t value)
{
__raw_bits_or((1<<5), 0x8B000008);
__raw_bits_or((1<<10), 0x8A000384);
__raw_bits_or((1<<10), 0x8A000388);
__raw_bits_or((1<<10), 0x8A000380);
}
static void sdhci_sprd_set_base_clock(unsigned int clock)
{
unsigned long flags;
/* don't bother if the clock is going off. */
if (clock == 0)
return;
if (clock > SDIO_MAX_CLK)
clock = SDIO_MAX_CLK;
//Select the clk source of SDIO
__raw_bits_and(~(BIT_17|BIT_18), GR_CLK_GEN5);
if (clock >= SDIO_BASE_CLK_96M) {
//default is 96M
;
} else if (clock >= SDIO_BASE_CLK_64M) {
__raw_bits_or((1<<17), GR_CLK_GEN5);
} else if (clock >= SDIO_BASE_CLK_48M) {
__raw_bits_or((2<<17), GR_CLK_GEN5);
} else {
__raw_bits_or((3<<17), GR_CLK_GEN5);
}
printf("after set sd clk, CLK_GEN5:%x\r\n",
__raw_readl(GR_CLK_GEN5));
return;
}
static int32_t sprdfb_dispc_early_init(struct sprdfb_device *dev)
{
FB_PRINT("sprdfb:[%s]\n", __FUNCTION__);
//select DISPC clock source
__raw_bits_and(~(1<<1), AHB_DISPC_CLK); //pll_src=256M
__raw_bits_and(~(1<<2), AHB_DISPC_CLK);
//set DISPC divdior
__raw_bits_and(~(1<<3), AHB_DISPC_CLK); //div=0
__raw_bits_and(~(1<<4), AHB_DISPC_CLK);
__raw_bits_and(~(1<<5), AHB_DISPC_CLK);
//select DBI clock source
__raw_bits_and(~(1<<9), AHB_DISPC_CLK); //pll_src=256M
__raw_bits_and(~(1<<10), AHB_DISPC_CLK);
//set DBI divdior
__raw_bits_and(~(1<<11), AHB_DISPC_CLK); //div=0
__raw_bits_and(~(1<<12), AHB_DISPC_CLK);
__raw_bits_and(~(1<<13), AHB_DISPC_CLK);
//select DPI clock source
__raw_bits_and(~(1<<17), AHB_DISPC_CLK); //pll_src=384M
__raw_bits_and(~(1<<18), AHB_DISPC_CLK);
//set DPI divdior
__raw_bits_and(~(1<<19), AHB_DISPC_CLK); //div=10, dpi_clk = pll_src/(10+1)
__raw_bits_or((1<<20), AHB_DISPC_CLK);
__raw_bits_and(~(1<<21), AHB_DISPC_CLK);
__raw_bits_or((1<<22), AHB_DISPC_CLK);
__raw_bits_and(~(1<<23), AHB_DISPC_CLK);
__raw_bits_and(~(1<<24), AHB_DISPC_CLK);
__raw_bits_and(~(1<<25), AHB_DISPC_CLK);
__raw_bits_and(~(1<<26), AHB_DISPC_CLK);
//enable dispc matric clock
__raw_bits_or((1<<9), AHB_CTL2); //core_clock_en
__raw_bits_or((1<<11), AHB_CTL2); //matrix clock en
//enable DISPC clock
__raw_bits_or(1<<22, AHB_CTL0);
printf("0x20900200 = 0x%x\n", __raw_readl(0x20900200));
printf("0x20900208 = 0x%x\n", __raw_readl(0x20900208));
printf("0x20900220 = 0x%x\n", __raw_readl(0x20900220));
dispc_reset();
dispc_module_enable();
is_first_frame = 1;
return 0;
}
static void usb_enable_module(int en)
{
if (en){
__raw_bits_or(BIT_6, AHB_CTL3);
__raw_bits_and(~BIT_9, GR_CLK_GEN5);
//__raw_bits_or(BIT_5, AHB_CTL0);
}else {
__raw_bits_and(~BIT_6, AHB_CTL3);
__raw_bits_or(BIT_9, GR_CLK_GEN5);
__raw_bits_and(~BIT_5, AHB_CTL0);
}
}
void udc_power_on(void)
{
__raw_bits_or(BIT_8, USB_PHY_CTRL);
__raw_bits_or(BIT_17, USB_PHY_CTRL);
__raw_bits_and(~BIT_16, USB_PHY_CTRL);
__raw_bits_and(~(BIT_13 | BIT_12), USB_PHY_CTRL);
__raw_bits_or(BIT_15 | BIT_14, USB_PHY_CTRL);
__raw_bits_and(~BIT_1, AHB_CTL3);
__raw_bits_and(~BIT_2, AHB_CTL3);
usb_startup();
}
static void usb_startup(void)
{
usb_enable_module(1);
dwc_mdelay(10);
usb_ldo_switch(0);
__raw_bits_and(~BIT_1, AHB_CTL3);
__raw_bits_and(~BIT_2, AHB_CTL3);
usb_ldo_switch(1);
__raw_bits_or(BIT_6, AHB_CTL3);
//__raw_bits_or(BIT_7, AHB_SOFT_RST);
//dwc_mdelay(10);
//__raw_bits_and(~BIT_7, AHB_SOFT_RST);
__raw_bits_or(BIT_5, AHB_CTL0);
dwc_mdelay(30);
}
void set_backlight(uint32_t brightness)
{
int index = PWM_INDEX;
__raw_bits_or((0x1 << 0), REG_AON_CLK_PWM0_CFG + index * 4);//ext_26m select
if (0 == brightness) {
pwm_write(index, 0, PWM_PRESCALE);
printf("sprd backlight power off. pwm_index=%d brightness=%d\n", index, brightness);
} else {
__raw_bits_or((0x1 << (index+4)), REG_AON_APB_APB_EB0); //PWMx EN
pwm_write(index, PWM2_SCALE, PWM_PRESCALE);
pwm_write(index, (brightness << 8) | PWM_MOD_MAX, PWM_CNT);
pwm_write(index, PWM_REG_MSK, PWM_PAT_LOW);
pwm_write(index, PWM_REG_MSK, PWM_PAT_HIG);
pwm_write(index, PWM_ENABLE, PWM_PRESCALE);
printf("sprd backlight power on. pwm_index=%d brightness=%d\n", index, brightness);
}
return;
}
int32_t sprdfb_dsi_init(struct sprdfb_device *dev)
{
dsih_error_t result = OK;
dsih_ctrl_t* dsi_instance = &(dsi_ctx.dsi_inst);
dphy_t *phy = &(dsi_instance->phy_instance);
struct info_mipi * mipi = dev->panel->info.mipi;
__raw_bits_or((1<<0), 0x2090021c); //enable dphy
FB_PRINT("sprdfb:[%s]\n", __FUNCTION__);
dsi_early_int();
phy->address = DSI_CTL_BEGIN;
phy->core_read_function = dsi_core_read_function;
phy->core_write_function = dsi_core_write_function;
phy->log_error = dsi_log_error;
phy->log_info = NULL;
phy->reference_freq = DSI_PHY_REF_CLOCK;
dsi_instance->address = DSI_CTL_BEGIN;
dsi_instance->color_mode_polarity =mipi->color_mode_pol;
dsi_instance->shut_down_polarity = mipi->shut_down_pol;
dsi_instance->core_read_function = dsi_core_read_function;
dsi_instance->core_write_function = dsi_core_write_function;
dsi_instance->log_error = dsi_log_error;
dsi_instance->log_info = NULL;
/*in our rtl implementation, this is max rd time, not bta time and use 15bits*/
dsi_instance->max_bta_cycles = 0x6000;//10;
dsi_instance->max_hs_to_lp_cycles = 4;//110;
dsi_instance->max_lp_to_hs_cycles = 15;//10;
dsi_instance->max_lanes = mipi->lan_number;
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_init();
}/*else{
dsi_dpi_init(dev->panel);
}*/
/*
result = mipi_dsih_unregister_all_events(dsi_instance);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_unregister_all_events fail (%d)!\n", __FUNCTION__, result);
return -1;
}
*/
dsi_core_write_function(DSI_CTL_BEGIN, R_DSI_HOST_ERROR_MSK0, 0x1fffff);
dsi_core_write_function(DSI_CTL_BEGIN, R_DSI_HOST_ERROR_MSK1, 0x3ffff);
result = mipi_dsih_open(dsi_instance);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_open fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_dphy_configure(phy, mipi->lan_number, mipi->phy_feq);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_dphy_configure fail (%d)!\n", __FUNCTION__, result);
return -1;
}
while(5 != (dsi_core_read_function(DSI_CTL_BEGIN, R_DSI_HOST_PHY_STATUS) & 5));
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_setbuswidth(mipi);
}
result = mipi_dsih_enable_rx(dsi_instance, 1);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_enable_rx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_ecc_rx(dsi_instance, 1);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_ecc_rx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_eotp_rx(dsi_instance, 1);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_eotp_rx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_eotp_tx(dsi_instance, 1);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_eotp_tx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
if(SPRDFB_MIPI_MODE_VIDEO == mipi->work_mode){
dsi_dpi_init(dev->panel);
}
return 0;
}
