Esempio n. 1
0
static inline void rt_intc_w32(u32 val, unsigned reg)
{
    __raw_writel(val, rt_intc_membase + reg);
}
Esempio n. 2
0
static inline void ehci_write(void __iomem *base, u32 reg, u32 val)
{
	__raw_writel(val, base + reg);
}
Esempio n. 3
0
static int
isl_upload_firmware(islpci_private *priv)
{
	u32 reg, rc;
	void __iomem *device_base = priv->device_base;

	/* clear the RAMBoot and the Reset bit */
	reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
	reg &= ~ISL38XX_CTRL_STAT_RESET;
	reg &= ~ISL38XX_CTRL_STAT_RAMBOOT;
	writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
	wmb();
	udelay(ISL38XX_WRITEIO_DELAY);

	/* set the Reset bit without reading the register ! */
	reg |= ISL38XX_CTRL_STAT_RESET;
	writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
	wmb();
	udelay(ISL38XX_WRITEIO_DELAY);

	/* clear the Reset bit */
	reg &= ~ISL38XX_CTRL_STAT_RESET;
	writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
	wmb();

	/* wait a while for the device to reboot */
	mdelay(50);

	{
		const struct firmware *fw_entry = NULL;
		long fw_len;
		const u32 *fw_ptr;

		rc = request_firmware(&fw_entry, priv->firmware, PRISM_FW_PDEV);
		if (rc) {
			printk(KERN_ERR
			       "%s: request_firmware() failed for '%s'\n",
			       "prism54", priv->firmware);
			return rc;
		}
		/* prepare the Direct Memory Base register */
		reg = ISL38XX_DEV_FIRMWARE_ADDRES;

		fw_ptr = (u32 *) fw_entry->data;
		fw_len = fw_entry->size;

		if (fw_len % 4) {
			printk(KERN_ERR
			       "%s: firmware '%s' size is not multiple of 32bit, aborting!\n",
			       "prism54", priv->firmware);
			release_firmware(fw_entry);
			return -EILSEQ; /* Illegal byte sequence  */;
		}

		while (fw_len > 0) {
			long _fw_len =
			    (fw_len >
			     ISL38XX_MEMORY_WINDOW_SIZE) ?
			    ISL38XX_MEMORY_WINDOW_SIZE : fw_len;
			u32 __iomem *dev_fw_ptr = device_base + ISL38XX_DIRECT_MEM_WIN;

			/* set the card's base address for writing the data */
			isl38xx_w32_flush(device_base, reg,
					  ISL38XX_DIR_MEM_BASE_REG);
			wmb();	/* be paranoid */

			/* increment the write address for next iteration */
			reg += _fw_len;
			fw_len -= _fw_len;

			/* write the data to the Direct Memory Window 32bit-wise */
			/* memcpy_toio() doesn't guarantee 32bit writes :-| */
			while (_fw_len > 0) {
				/* use non-swapping writel() */
				__raw_writel(*fw_ptr, dev_fw_ptr);
				fw_ptr++, dev_fw_ptr++;
				_fw_len -= 4;
			}

			/* flush PCI posting */
			(void) readl(device_base + ISL38XX_PCI_POSTING_FLUSH);
			wmb();	/* be paranoid again */

			BUG_ON(_fw_len != 0);
		}

		BUG_ON(fw_len != 0);

		/* Firmware version is at offset 40 (also for "newmac") */
		printk(KERN_DEBUG "%s: firmware version: %.8s\n",
		       priv->ndev->name, fw_entry->data + 40);

		release_firmware(fw_entry);
	}

	/* now reset the device
	 * clear the Reset & ClkRun bit, set the RAMBoot bit */
	reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
	reg &= ~ISL38XX_CTRL_STAT_CLKRUN;
	reg &= ~ISL38XX_CTRL_STAT_RESET;
	reg |= ISL38XX_CTRL_STAT_RAMBOOT;
	isl38xx_w32_flush(device_base, reg, ISL38XX_CTRL_STAT_REG);
	wmb();
	udelay(ISL38XX_WRITEIO_DELAY);

	/* set the reset bit latches the host override and RAMBoot bits
	 * into the device for operation when the reset bit is reset */
	reg |= ISL38XX_CTRL_STAT_RESET;
	writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
	/* don't do flush PCI posting here! */
	wmb();
	udelay(ISL38XX_WRITEIO_DELAY);

	/* clear the reset bit should start the whole circus */
	reg &= ~ISL38XX_CTRL_STAT_RESET;
	writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
	/* don't do flush PCI posting here! */
	wmb();
	udelay(ISL38XX_WRITEIO_DELAY);

	return 0;
}
Esempio n. 4
0
static void __init jive_machine_init(void)
{
	/* register system devices for managing low level suspend */

	sysdev_class_register(&jive_pm_sysclass);
	sysdev_register(&jive_pm_sysdev);

	/* write our sleep configurations for the IO. Pull down all unused
	 * IO, ensure that we have turned off all peripherals we do not
	 * need, and configure the ones we do need. */

	/* Port B sleep */

	__raw_writel(S3C2412_SLPCON_IN(0)   |
		     S3C2412_SLPCON_PULL(1) |
		     S3C2412_SLPCON_HIGH(2) |
		     S3C2412_SLPCON_PULL(3) |
		     S3C2412_SLPCON_PULL(4) |
		     S3C2412_SLPCON_PULL(5) |
		     S3C2412_SLPCON_PULL(6) |
		     S3C2412_SLPCON_HIGH(7) |
		     S3C2412_SLPCON_PULL(8) |
		     S3C2412_SLPCON_PULL(9) |
		     S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);

	/* Port C sleep */

	__raw_writel(S3C2412_SLPCON_PULL(0) |
		     S3C2412_SLPCON_PULL(1) |
		     S3C2412_SLPCON_PULL(2) |
		     S3C2412_SLPCON_PULL(3) |
		     S3C2412_SLPCON_PULL(4) |
		     S3C2412_SLPCON_PULL(5) |
		     S3C2412_SLPCON_LOW(6)  |
		     S3C2412_SLPCON_PULL(6) |
		     S3C2412_SLPCON_PULL(7) |
		     S3C2412_SLPCON_PULL(8) |
		     S3C2412_SLPCON_PULL(9) |
		     S3C2412_SLPCON_PULL(10) |
		     S3C2412_SLPCON_PULL(11) |
		     S3C2412_SLPCON_PULL(12) |
		     S3C2412_SLPCON_PULL(13) |
		     S3C2412_SLPCON_PULL(14) |
		     S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);

	/* Port D sleep */

	__raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);

	/* Port F sleep */

	__raw_writel(S3C2412_SLPCON_LOW(0)  |
		     S3C2412_SLPCON_LOW(1)  |
		     S3C2412_SLPCON_LOW(2)  |
		     S3C2412_SLPCON_EINT(3) |
		     S3C2412_SLPCON_EINT(4) |
		     S3C2412_SLPCON_EINT(5) |
		     S3C2412_SLPCON_EINT(6) |
		     S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);

	/* Port G sleep */

	__raw_writel(S3C2412_SLPCON_IN(0)    |
		     S3C2412_SLPCON_IN(1)    |
		     S3C2412_SLPCON_IN(2)    |
		     S3C2412_SLPCON_IN(3)    |
		     S3C2412_SLPCON_IN(4)    |
		     S3C2412_SLPCON_IN(5)    |
		     S3C2412_SLPCON_IN(6)    |
		     S3C2412_SLPCON_IN(7)    |
		     S3C2412_SLPCON_PULL(8)  |
		     S3C2412_SLPCON_PULL(9)  |
		     S3C2412_SLPCON_IN(10)   |
		     S3C2412_SLPCON_PULL(11) |
		     S3C2412_SLPCON_PULL(12) |
		     S3C2412_SLPCON_PULL(13) |
		     S3C2412_SLPCON_IN(14)   |
		     S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);

	/* Port H sleep */

	__raw_writel(S3C2412_SLPCON_PULL(0) |
		     S3C2412_SLPCON_PULL(1) |
		     S3C2412_SLPCON_PULL(2) |
		     S3C2412_SLPCON_PULL(3) |
		     S3C2412_SLPCON_PULL(4) |
		     S3C2412_SLPCON_PULL(5) |
		     S3C2412_SLPCON_PULL(6) |
		     S3C2412_SLPCON_IN(7)   |
		     S3C2412_SLPCON_IN(8)   |
		     S3C2412_SLPCON_PULL(9) |
		     S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);

	/* initialise the power management now we've setup everything. */

	s3c2410_pm_init();

	s3c_device_nand.dev.platform_data = &jive_nand_info;

	/* initialise the spi */

	s3c2410_gpio_setpin(S3C2410_GPG13, 0);
	s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);

	s3c2410_gpio_setpin(S3C2410_GPB7, 1);
	s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);

	s3c2410_gpio_setpin(S3C2410_GPB6, 0);
	s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);

	s3c2410_gpio_setpin(S3C2410_GPG8, 1);
	s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);

	/* initialise the WM8750 spi */

	s3c2410_gpio_setpin(S3C2410_GPH10, 1);
	s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);

	/* Turn off suspend on both USB ports, and switch the
	 * selectable USB port to USB device mode. */

	s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
			      S3C2410_MISCCR_USBSUSPND0 |
			      S3C2410_MISCCR_USBSUSPND1, 0x0);

	s3c24xx_udc_set_platdata(&jive_udc_cfg);
	s3c24xx_fb_set_platdata(&jive_lcd_config);

	spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));

	s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
	i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));

	pm_power_off = jive_power_off;

	platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
}
Esempio n. 5
0
static int magus_pm_suspend(void)
{
	void (*magus_cpu_suspend_ptr) (void);
	local_irq_disable();
	local_fiq_disable();

	/* 1. Copy suspend code to internal SRAM */
	/* saving portion of SRAM to be used by suspend function. */
	memcpy(saved_sram, (void *)SRAM_VA, magus_cpu_suspend_sz);

	/*make sure SRAM copy gets physically written into SDRAM.
	SDRAM will be placed into self-refresh during power down */
	flush_cache_all();

	/*copy suspend function into SRAM */
	memcpy((void *)SRAM_VA, magus_cpu_suspend, magus_cpu_suspend_sz);
	
	//magus_pm_debug("Status before save");
	/*2. Save and Disable interrupts except for the wake events */
	magus_pm_save_registers();
	magus_pm_disable_int();	

	/* Shutdown PLL2 */
	__raw_writel((__raw_readl(SCRM_PLL2R) | 0x1), SCRM_PLL2R); //PD3 Powerkey
	
	/*2.1 . Enable wake-up events */
	/* set the irq configuration for wake */
    magus_pm_configure_extint();
	
	/*3. Disable and save other modules */
	diable_external_device();

	magus_pm_debug("Status before suspend");

	/* Must wait for serial buffers to clear */
	mdelay(200);
	/*make sure SRAM copy gets physically written into SDRAM.
	SDRAM will be placed into self-refresh during power down */
	/*4. do suspend */
	/* Jump to SRAM suspend code */
	if(1){
	//if(enable_dyn_sleep){ //For debug.
		flush_cache_all();
		magus_cpu_suspend_ptr = (void *)SRAM_VA;
		magus_cpu_suspend_ptr();
	}

	magus_pm_debug("Status after wake up");
	/*4.1.  Disable and save other modules */
	restore_external_device();	
	
	magus_pm_restore_registers();
	magus_pm_debug("Status after restore");

	/*5. restoring portion of SRAM that was used by suspend function */
    memcpy((void *)SRAM_VA, saved_sram, magus_cpu_suspend_sz);

	/*6. Restore interrupts */
	local_fiq_enable();
	local_irq_enable();
	return 0;
}
Esempio n. 6
0
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
{
	int offs = eint_offset(irq);
	int shift;
	u32 ctrl, mask;
	u32 newvalue = 0;

	switch (type) {
	case IRQ_TYPE_NONE:
		printk(KERN_WARNING "No edge setting!\n");
		break;

	case IRQ_TYPE_EDGE_RISING:
		newvalue = S5P_EXTINT_RISEEDGE;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		newvalue = S5P_EXTINT_FALLEDGE;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		newvalue = S5P_EXTINT_BOTHEDGE;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		newvalue = S5P_EXTINT_LOWLEV;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		newvalue = S5P_EXTINT_HILEV;
		break;

	default:
		printk(KERN_ERR "No such irq type %d", type);
		return -1;
	}

	shift = (offs & 0x7) * 4;
	mask = 0x7 << shift;

	ctrl = __raw_readl(S5PC11X_EINTCON(eint_conf_reg(irq)));
	ctrl &= ~mask;
	ctrl |= newvalue << shift;
	__raw_writel(ctrl, S5PC11X_EINTCON(eint_conf_reg(irq)));
#ifdef  S5PC11X_ALIVEGPIO_STORE
	ctrl = __raw_readl(S5PC11X_EINTCON(eint_conf_reg(irq)));
#endif

	if((0 <= offs) && (offs < 8))
		s3c_gpio_cfgpin(S5PC11X_GPH0(offs&0x7), 0xf<<((offs&0x7)*4));
	else if((8 <= offs) && (offs < 16))
		s3c_gpio_cfgpin(S5PC11X_GPH1(offs&0x7), 0xf<<((offs&0x7)*4));
	else if((16 <= offs) && (offs < 24))
		s3c_gpio_cfgpin(S5PC11X_GPH2(offs&0x7), 0xf<<((offs&0x7)*4));
	else if((24 <= offs) && (offs < 32))
		s3c_gpio_cfgpin(S5PC11X_GPH3(offs&0x7), 0xf<<((offs&0x7)*4));
	else
		printk(KERN_ERR "No such irq number %d", offs);

	return 0;
}
Esempio n. 7
0
static inline void lcdc_write(unsigned int val, unsigned int addr)
{
	__raw_writel(val, da8xx_fb_reg_base + (addr));
}
Esempio n. 8
0
void exynos_ppmu_stop(void __iomem *ppmu_base)
{
	__raw_writel(PPMU_DISABLE, ppmu_base);
}
static __init void da850_evm_init(void)
{
	int ret;

	ret = pmic_tps65070_init();
	if (ret)
		pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",
				ret);

	ret = da850_register_edma(da850_edma_rsv);
	if (ret)
		pr_warning("da850_evm_init: edma registration failed: %d\n",
				ret);

	ret = davinci_cfg_reg_list(da850_i2c0_pins);
	if (ret)
		pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
				ret);

	ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
	if (ret)
		pr_warning("da850_evm_init: i2c0 registration failed: %d\n",
				ret);


	ret = da8xx_register_watchdog();
	if (ret)
		pr_warning("da830_evm_init: watchdog registration failed: %d\n",
				ret);

	if (HAS_MMC) {
		ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
		if (ret)
			pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
					" %d\n", ret);

		ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n");
		if (ret)
			pr_warning("da850_evm_init: can not open GPIO %d\n",
					DA850_MMCSD_CD_PIN);
		gpio_direction_input(DA850_MMCSD_CD_PIN);

		ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n");
		if (ret)
			pr_warning("da850_evm_init: can not open GPIO %d\n",
					DA850_MMCSD_WP_PIN);
		gpio_direction_input(DA850_MMCSD_WP_PIN);

		ret = da8xx_register_mmcsd0(&da850_mmc_config);
		if (ret)
			pr_warning("da850_evm_init: mmcsd0 registration failed:"
					" %d\n", ret);

		ret = da850_wl12xx_init();
		if (ret)
			pr_warning("da850_evm_init: wl12xx initialization"
				   " failed: %d\n", ret);
	}

	davinci_serial_init(&da850_evm_uart_config);

	i2c_register_board_info(1, da850_evm_i2c_devices,
			ARRAY_SIZE(da850_evm_i2c_devices));

	/*
	 * shut down uart 0 and 1; they are not used on the board and
	 * accessing them causes endless "too much work in irq53" messages
	 * with arago fs
	 */
	__raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
	__raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);

	ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
	if (ret)
		pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
				ret);

	da8xx_register_mcasp(0, &da850_evm_snd_data);

	ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
	if (ret)
		pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
				ret);

	/* Handle board specific muxing for LCD here */
	ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
	if (ret)
		pr_warning("da850_evm_init: evm specific lcd mux setup "
				"failed: %d\n",	ret);

	ret = da850_lcd_hw_init();
	if (ret)
		pr_warning("da850_evm_init: lcd initialization failed: %d\n",
				ret);

	sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl,
	ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
	if (ret)
		pr_warning("da850_evm_init: lcdc registration failed: %d\n",
				ret);

	ret = da8xx_register_rtc();
	if (ret)
		pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);

	ret = da850_evm_init_cpufreq();
	if (ret)
		pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
				ret);

	ret = da8xx_register_cpuidle();
	if (ret)
		pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
				ret);

	ret = da850_register_pm(&da850_pm_device);
	if (ret)
		pr_warning("da850_evm_init: suspend registration failed: %d\n",
				ret);

	ret = da8xx_register_spi(1, da850evm_spi_info,
				 ARRAY_SIZE(da850evm_spi_info));
	if (ret)
		pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
				ret);

	ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
	if (ret)
		pr_warning("da850_evm_init: sata registration failed: %d\n",
				ret);

	da850_evm_setup_mac_addr();
}
Esempio n. 10
0
void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch,
			unsigned int evt)
{
	__raw_writel(evt, ppmu_base + PPMU_BEVTSEL(ch));
}
Esempio n. 11
0
void exynos_ppmu_start(void __iomem *ppmu_base)
{
	__raw_writel(PPMU_ENABLE, ppmu_base);
}
Esempio n. 12
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static void cam_write(struct omap1_cam_dev *pcdev, u16 reg, u32 val)
{
	pcdev->reg_cache[reg / sizeof(u32)] = val;
	__raw_writel(val, pcdev->base + reg);
}
Esempio n. 13
0
void init_ddr_settings(void)
{
	unsigned long iram_paddr;
	unsigned int reg;
	int i;
	struct clk *ddr_clk = clk_get(NULL, "ddr_clk");

	databahn_base = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K);

	/* Find the memory type, LPDDR2 or mddr. */
	mx50_ddr_type = __raw_readl(databahn_base) & 0xF00;
	if (mx50_ddr_type == MX50_LPDDR2) {
		normal_databahn_settings = lpddr2_databhan_regs_offsets;
		ddr_settings_size = ARRAY_SIZE(lpddr2_databhan_regs_offsets);
		}
	else if (mx50_ddr_type == MX50_MDDR) {
		normal_databahn_settings = mddr_databhan_regs_offsets;
		ddr_settings_size = ARRAY_SIZE(mddr_databhan_regs_offsets);
	} else {
		printk(KERN_DEBUG
		"%s: Unsupported memory type\n", __func__);
		return;
	}

	/* Copy the databhan settings into the iram location. */
	for (i = 0; i < ddr_settings_size; i++) {
			normal_databahn_settings[i][1] =
				__raw_readl(databahn_base
				+ normal_databahn_settings[i][0]);
		}
	/* Store the size of the array in iRAM also,
	 * increase the size by 8 bytes.
	 */
	iram_ddr_settings = iram_alloc(ddr_settings_size + 8, &iram_paddr);
	if (iram_ddr_settings == NULL) {
			printk(KERN_DEBUG
			"%s: failed to allocate iRAM memory for ddr settings\n",
			__func__);
			return;
	}

	/* Allocate IRAM for the DDR freq change code. */
	iram_alloc(SZ_8K, &iram_paddr);
	/* Need to remap the area here since we want the memory region
		 to be executable. */
	ddr_freq_change_iram_base = __arm_ioremap(iram_paddr,
						SZ_8K, MT_MEMORY);
	memcpy(ddr_freq_change_iram_base, mx50_ddr_freq_change, SZ_8K);
	change_ddr_freq = (void *)ddr_freq_change_iram_base;

	qosc_base = ioremap(MX50_QOSC_BASE_ADDR, SZ_4K);
	/* Enable the QoSC */
	reg = __raw_readl(qosc_base);
	reg &= ~0xC0000000;
	__raw_writel(reg, qosc_base);

	/* Allocate IRAM to run the WFI code from iram, since
	 * we can turn off the DDR clocks when ARM is in WFI.
	 */
	iram_alloc(SZ_4K, &iram_paddr);
	/* Need to remap the area here since we want the memory region
		 to be executable. */
	wait_in_iram_base = __arm_ioremap(iram_paddr,
						SZ_4K, MT_MEMORY);
	memcpy(wait_in_iram_base, mx50_wait, SZ_4K);
	wait_in_iram = (void *)wait_in_iram_base;

	clk_enable(ddr_clk);

	/* Set the DDR to enter automatic self-refresh. */
	/* Set the DDR to automatically enter lower power mode 4. */
	reg = __raw_readl(databahn_base + DATABAHN_CTL_REG22);
	reg &= ~LOWPOWER_AUTOENABLE_MASK;
	reg |= 1 << 1;
	__raw_writel(reg, databahn_base + DATABAHN_CTL_REG22);

	/* set the counter for entering mode 4. */
	reg = __raw_readl(databahn_base + DATABAHN_CTL_REG21);
	reg &= ~LOWPOWER_EXTERNAL_CNT_MASK;
	reg = 128 << LOWPOWER_EXTERNAL_CNT_OFFSET;
	__raw_writel(reg, databahn_base + DATABAHN_CTL_REG21);

	/* Enable low power mode 4 */
	reg = __raw_readl(databahn_base + DATABAHN_CTL_REG20);
	reg &= ~LOWPOWER_CONTROL_MASK;
	reg |= 1 << 1;
	__raw_writel(reg, databahn_base + DATABAHN_CTL_REG20);
	clk_disable(ddr_clk);

	epdc_clk = clk_get(NULL, "epdc_axi");
	if (IS_ERR(epdc_clk)) {
		printk(KERN_DEBUG "%s: failed to get epdc_axi_clk\n",
			__func__);
		return;
	}
}
Esempio n. 14
0
int update_ddr_freq(int ddr_rate)
{
	int i;
	unsigned int reg;

	if (!can_change_ddr_freq())
		return -1;

	local_flush_tlb_all();
	flush_cache_all();

	iram_ddr_settings[0][0] = ddr_settings_size;
	if (ddr_rate == LP_APM_CLK) {
		if (mx50_ddr_type == MX50_LPDDR2) {
			for (i = 0; i < iram_ddr_settings[0][0]; i++) {
				iram_ddr_settings[i + 1][0] =
								lpddr2_24[i][0];
				iram_ddr_settings[i + 1][1] =
								lpddr2_24[i][1];
			}
		} else {
			for (i = 0; i < iram_ddr_settings[0][0]; i++) {
				iram_ddr_settings[i + 1][0]
								= mddr_24[i][0];
				iram_ddr_settings[i + 1][1]
								= mddr_24[i][1];
			}
		}
	} else {
		for (i = 0; i < iram_ddr_settings[0][0]; i++) {
			iram_ddr_settings[i + 1][0] =
					normal_databahn_settings[i][0];
			iram_ddr_settings[i + 1][1] =
					normal_databahn_settings[i][1];
		}
		if (ddr_rate == ddr_med_rate) {
			/*Change the tref setting */
			for (i = 0; i < iram_ddr_settings[0][0]; i++) {
				if (iram_ddr_settings[i + 1][0] == 0x40) {
					if (mx50_ddr_type == MX50_LPDDR2)
						/* LPDDR2 133MHz. */
						iram_ddr_settings[i + 1][1] =
								0x00050180;
					else
						/* mDDR 133MHz. */
						iram_ddr_settings[i + 1][1] =
								0x00050208;
					break;
				}
			}
		}
	}
	/* Disable all masters from accessing the DDR. */
	reg = __raw_readl(qosc_base + HW_QOS_DISABLE);
	reg |= 0xFFE;
	__raw_writel(reg, qosc_base + HW_QOS_DISABLE_SET);
	udelay(100);

	/* Set the DDR to default freq. */
	change_ddr_freq(ccm_base, databahn_base, ddr_rate,
					iram_ddr_settings);

	/* Enable all masters to access the DDR. */
	__raw_writel(reg, qosc_base + HW_QOS_DISABLE_CLR);

	return 0;
}
void l2_cache_init(void)
{
	/* Enable L2 cache */
	__raw_writel(L2_CACHE_ENABLE, RAMCR);
}
Esempio n. 16
0
void mx6_cpu_regulator_init(void)
{
	int cpu;
	u32 curr_cpu = 0;
	unsigned int reg;
#ifndef CONFIG_SMP
	unsigned long old_loops_per_jiffy;
#endif
	void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);

	if (initialized)
		return;

	initialized = true;

	external_pureg = 0;
	/*If internal ldo actived, use internal cpu_* regulator to replace the
	*regulator ids from board file. If internal ldo bypassed, use the
	*regulator ids which defined in board file and source from extern pmic
	*power rails.
	*If you want to use ldo bypass,you should do:
	*1.set enable_ldo_mode=LDO_MODE_BYPASSED in your board file by default
	*   or set in commandline from u-boot
	*2.set your extern pmic regulator name in your board file.
	*/
	if (enable_ldo_mode != LDO_MODE_BYPASSED) {
		gp_reg_id = "cpu_vddgp";
		soc_reg_id = "cpu_vddsoc";
		pu_reg_id = "cpu_vddgpu";
	}
	printk(KERN_INFO "cpu regulator mode:%s\n", (enable_ldo_mode ==
		LDO_MODE_BYPASSED) ? "ldo_bypass" : "ldo_enable");
	cpu_regulator = regulator_get(NULL, gp_reg_id);
	if (IS_ERR(cpu_regulator))
		printk(KERN_ERR "%s: failed to get cpu regulator\n", __func__);
	else {
		cpu_clk = clk_get(NULL, "cpu_clk");
		if (IS_ERR(cpu_clk)) {
			printk(KERN_ERR "%s: failed to get cpu clock\n",
			       __func__);
		} else {
			curr_cpu = clk_get_rate(cpu_clk);
			cpu_op_tbl = get_cpu_op(&cpu_op_nr);

			soc_regulator = regulator_get(NULL, soc_reg_id);
			if (IS_ERR(soc_regulator))
				printk(KERN_ERR "%s: failed to get soc regulator\n",
					__func__);
			else
				/* set soc to highest setpoint voltage. */
				regulator_set_voltage(soc_regulator,
					      cpu_op_tbl[0].soc_voltage,
					      cpu_op_tbl[0].soc_voltage);

			pu_regulator = regulator_get(NULL, pu_reg_id);
			if (IS_ERR(pu_regulator))
				printk(KERN_ERR "%s: failed to get pu regulator\n",
					__func__);
			else
				/* set pu to higheset setpoint voltage. */
				regulator_set_voltage(pu_regulator,
					      cpu_op_tbl[0].pu_voltage,
					      cpu_op_tbl[0].pu_voltage);
			/* set the core to higheset setpoint voltage. */
			regulator_set_voltage(cpu_regulator,
					      cpu_op_tbl[0].cpu_voltage,
					      cpu_op_tbl[0].cpu_voltage);
			if (enable_ldo_mode == LDO_MODE_BYPASSED) {
				/* digital bypass VDDPU/VDDSOC/VDDARM */
				reg = __raw_readl(ANADIG_REG_CORE);
				reg &= ~BM_ANADIG_REG_CORE_REG0_TRG;
				reg |= BF_ANADIG_REG_CORE_REG0_TRG(0x1f);
				reg &= ~BM_ANADIG_REG_CORE_REG1_TRG;
				reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f);
				reg &= ~BM_ANADIG_REG_CORE_REG2_TRG;
				reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x1f);
				__raw_writel(reg, ANADIG_REG_CORE);
				/* mask the ANATOP brown out irq in the GPC. */
				reg = __raw_readl(gpc_base + 0x14);
				reg |= 0x80000000;
				__raw_writel(reg, gpc_base + 0x14);
			}

			clk_set_rate(cpu_clk, cpu_op_tbl[0].cpu_rate);

			/* fix loops-per-jiffy */
#ifdef CONFIG_SMP
			for_each_online_cpu(cpu)
				per_cpu(cpu_data, cpu).loops_per_jiffy =
				mx6_cpu_jiffies(
					per_cpu(cpu_data, cpu).loops_per_jiffy,
					curr_cpu / 1000,
					clk_get_rate(cpu_clk) / 1000);
#else
			old_loops_per_jiffy = loops_per_jiffy;

			loops_per_jiffy =
				mx6_cpu_jiffies(old_loops_per_jiffy,
						curr_cpu/1000,
						clk_get_rate(cpu_clk) / 1000);
#endif
#if defined(CONFIG_CPU_FREQ)
			/* Fix CPU frequency for CPUFREQ. */
			for (cpu = 0; cpu < num_online_cpus(); cpu++)
				cpufreq_get(cpu);
#endif
		}
	}
	/*
	 * if use ldo bypass and VDDPU_IN is single supplied
	 * by external pmic, it means VDDPU_IN can be turned off
	 * if GPU/VPU driver not running.In this case we should set
	 * external_pureg which can be used in pu_enable/pu_disable of
	 * arch/arm/mach-mx6/mx6_anatop_regulator.c to
	 * enable or disable external VDDPU regulator from pmic. But for FSL
	 * reference boards, VDDSOC_IN connect with VDDPU_IN, so we didn't set
	 * pu_reg_id to the external pmic regulator supply name in the board
	 * file. In this case external_pureg should be 0 and can't turn off
	 * extern pmic regulator, but can turn off VDDPU by internal anatop
	 * power gate.
	 *
	 * if enable internal ldo , external_pureg will be 0, and
	 * VDDPU can be turned off by internal anatop anatop power gate.
	 *
	 */
	if (!IS_ERR(pu_regulator) && strcmp(pu_reg_id, "cpu_vddgpu"))
		external_pureg = 1;
}
Esempio n. 17
0
void init_display_gpio_exynos(void)
{
	unsigned int reg = 0;

#if defined(CONFIG_S5P_DP)
	unsigned gpio_dp_hotplug = 0;

	gpio_dp_hotplug = get_display_dp_hotplug_gpio_exynos();
	/* Set Hotplug detect for DP */
	gpio_request(gpio_dp_hotplug, "dp_hotplug");
	/* TO DO */
	s3c_gpio_cfgpin(gpio_dp_hotplug, S3C_GPIO_SFN(3));
#endif

	/*
	 * Set DISP1BLK_CFG register for Display path selection
	 *
	 * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
	 * ---------------------
	 *  1 | FIMD : selected
	 */
	reg = __raw_readl(S3C_VA_SYS + 0x0214);
	reg &= ~(1 << 15);	/* To save other reset values */
	reg |= (1 << 15);
	__raw_writel(reg, S3C_VA_SYS + 0x0214);
#if defined(CONFIG_S5P_DP)
	/* Reference clcok selection for DPTX_PHY: PAD_OSC_IN */
	reg = __raw_readl(S3C_VA_SYS + 0x04d4);
	reg &= ~(1 << 0);
	__raw_writel(reg, S3C_VA_SYS + 0x04d4);

	/* DPTX_PHY: XXTI */
	reg = __raw_readl(S3C_VA_SYS + 0x04d8);
	reg &= ~(1 << 3);
	__raw_writel(reg, S3C_VA_SYS + 0x04d8);
#endif
	/*
	 * Set DISP1BLK_CFG register for Display path selection
	 *
	 * MIC of DISP1_BLK Bypass selection: DISP1BLK_CFG[11]
	 * --------------------
	 *  0 | MIC
	 *  1 | Bypass : selected
	 */
	reg = __raw_readl(S3C_VA_SYS + 0x0214);
	reg &= ~(1 << 11);
#ifndef CONFIG_DECON_MIC
	reg |= (1 << 11);
#endif
	__raw_writel(reg, S3C_VA_SYS + 0x0214);

#if  defined (CONFIG_FB_I80_COMMAND_MODE) && !defined (FIMD_VIDEO_PSR)
	reg = __raw_readl(S3C_VA_SYS + 0x0214);
	reg |= (1 << 24);
	__raw_writel(reg, S3C_VA_SYS + 0x0214);
#endif

#if defined (CONFIG_SOC_EXYNOS5422_REV_0)
	/* related to convertor between FIMD & MIPI */
	reg = __raw_readl(S3C_VA_SYS + 0x0214);
	reg |= (1 << 12);
	__raw_writel(reg, S3C_VA_SYS + 0x0214);
#endif

}
Esempio n. 18
0
static inline void dss_write_reg(const struct dss_reg idx, u32 val)
{
    __raw_writel(val, dss.base + idx.idx);
}
Esempio n. 19
0
static inline void greth_write_bd(u32 *bd, u32 val)
{
	__raw_writel(cpu_to_be32(val), bd);
}
Esempio n. 20
0
/*
 * Initialize the power management subsystem.
 *
 * Return value:
 *      -ENODEV: initialization failed
 *      0: success
 */
static int __init msm_pm_init(void)
{
	int ret;
	int val;
	enum msm_pm_time_stats_id enable_stats[] = {
		MSM_PM_STAT_REQUESTED_IDLE,
		MSM_PM_STAT_IDLE_SPIN,
		MSM_PM_STAT_IDLE_WFI,
		MSM_PM_STAT_IDLE_STANDALONE_POWER_COLLAPSE,
		MSM_PM_STAT_IDLE_FAILED_STANDALONE_POWER_COLLAPSE,
		MSM_PM_STAT_IDLE_POWER_COLLAPSE,
		MSM_PM_STAT_IDLE_FAILED_POWER_COLLAPSE,
		MSM_PM_STAT_SUSPEND,
		MSM_PM_STAT_FAILED_SUSPEND,
		MSM_PM_STAT_NOT_IDLE,
	};

#ifdef CONFIG_CPU_V7
	pgd_t *pc_pgd;
	pmd_t *pmd;
	unsigned long pmdval;
	unsigned long exit_phys;

	exit_phys = virt_to_phys(msm_pm_collapse_exit);

	/* Page table for cores to come back up safely. */
	pc_pgd = pgd_alloc(&init_mm);
	if (!pc_pgd)
		return -ENOMEM;
	pmd = pmd_offset(pud_offset(pc_pgd + pgd_index(exit_phys), exit_phys),
			 exit_phys);
	pmdval = (exit_phys & PGDIR_MASK) |
		     PMD_TYPE_SECT | PMD_SECT_AP_WRITE;
	pmd[0] = __pmd(pmdval);
	pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));

	msm_saved_state_phys =
		allocate_contiguous_ebi_nomap(CPU_SAVED_STATE_SIZE *
					      num_possible_cpus(), 4);
	if (!msm_saved_state_phys)
		return -ENOMEM;
	msm_saved_state = ioremap_nocache(msm_saved_state_phys,
					  CPU_SAVED_STATE_SIZE *
					  num_possible_cpus());
	if (!msm_saved_state)
		return -ENOMEM;

	/* It is remotely possible that the code in msm_pm_collapse_exit()
	 * which turns on the MMU with this mapping is in the
	 * next even-numbered megabyte beyond the
	 * start of msm_pm_collapse_exit().
	 * Map this megabyte in as well.
	 */
	pmd[2] = __pmd(pmdval + (2 << (PGDIR_SHIFT - 1)));
	flush_pmd_entry(pmd);
	msm_pm_pc_pgd = virt_to_phys(pc_pgd);
	clean_caches((unsigned long)&msm_pm_pc_pgd, sizeof(msm_pm_pc_pgd),
		     virt_to_phys(&msm_pm_pc_pgd));
#endif

	msm_pm_smem_data = smem_alloc(SMEM_APPS_DEM_SLAVE_DATA,
		sizeof(*msm_pm_smem_data));
	if (msm_pm_smem_data == NULL) {
		printk(KERN_ERR "%s: failed to get smsm_data\n", __func__);
		return -ENODEV;
	}

	ret = msm_timer_init_time_sync(msm_pm_timeout);
	if (ret)
		return ret;

	ret = smsm_change_intr_mask(SMSM_POWER_MASTER_DEM, 0xFFFFFFFF, 0);
	if (ret) {
		printk(KERN_ERR "%s: failed to clear interrupt mask, %d\n",
			__func__, ret);
		return ret;
	}

	if (cpu_is_msm8625()) {
		target_type = TARGET_IS_8625;
		clean_caches((unsigned long)&target_type, sizeof(target_type),
				virt_to_phys(&target_type));

		/*
		 * Configure the MPA5_GDFS_CNT_VAL register for
		 * DBGPWRUPEREQ_OVERRIDE[17:16] = Override the
		 * DBGNOPOWERDN for each cpu.
		 * MPA5_GDFS_CNT_VAL[9:0] = Delay counter for
		 * GDFS control.
		 */
		val = 0x00030002;
		__raw_writel(val, (MSM_CFG_CTL_BASE + 0x38));

		l2x0_base_addr = MSM_L2CC_BASE;
	}

#ifdef CONFIG_MSM_MEMORY_LOW_POWER_MODE
	/* The wakeup_reason field is overloaded during initialization time
	   to signal Modem that Apps will control the low power modes of
	   the memory.
	 */
	msm_pm_smem_data->wakeup_reason = 1;
	smsm_change_state(SMSM_APPS_DEM, 0, DEM_SLAVE_SMSM_RUN);
#endif

	BUG_ON(msm_pm_modes == NULL);

	suspend_set_ops(&msm_pm_ops);

	msm_pm_mode_sysfs_add();
	msm_pm_add_stats(enable_stats, ARRAY_SIZE(enable_stats));

	atomic_set(&msm_pm_init_done, 1);
	return 0;
}
Esempio n. 21
0
static int jive_pm_resume(struct sys_device *sd)
{
	__raw_writel(0x0, S3C2412_INFORM0);
	return 0;
}
Esempio n. 22
0
/*
 * Program the top csr from core0 context to put the
 * core1 into GDFS, as core1 is not running yet.
 */
static void configure_top_csr(void)
{
	void __iomem *base_ptr;
	unsigned int value = 0;

	base_ptr = core1_reset_base();
	if (!base_ptr)
		return;

	/* bring the core1 out of reset */
	__raw_writel(0x3, base_ptr);
	mb();
	/*
	 * override DBGNOPOWERDN and program the GDFS
	 * count val
	 */

	 __raw_writel(0x00030002, (MSM_CFG_CTL_BASE + 0x38));
	mb();

	/* Initialize the SPM0 and SPM1 registers */
	msm_spm_reinit();

	/* enable TCSR for core1 */
	value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
	value |= BIT(22);
	__raw_writel(value,  MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
	mb();

	/* set reset bit for SPM1 */
	value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
	value |= BIT(20);
	__raw_writel(value,  MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
	mb();

	/* set CLK_OFF bit */
	value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
	value |= BIT(18);
	__raw_writel(value,  MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
	mb();

	/* set clamps bit */
	value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
	value |= BIT(21);
	__raw_writel(value,  MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
	mb();

	/* set power_up bit */
	value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
	value |= BIT(19);
	__raw_writel(value,  MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
	mb();

	/* Disable TSCR for core0 */
	value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
	value &= ~BIT(22);
	__raw_writel(value,  MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
	mb();
	__raw_writel(0x0, base_ptr);
	mb();
}
Esempio n. 23
0
static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data)
	{ __raw_writel(data, addr + offset); }
Esempio n. 24
0
void omap_writel(u32 v, u32 pa)
{
	__raw_writel(v, OMAP1_IO_ADDRESS(pa));
}
Esempio n. 25
0
static int s3c_mfc_resume(struct platform_device *pdev)
{

	int 		i, index = 0;
	int         	inst_no;
	int		is_mfc_on = 0;
	unsigned int	mfc_pwr, dwMfcBase;
	unsigned int	domain_v_ready;
	
	s3c_mfc_inst_context_t *mfcinst_ctx;

	mutex_lock(s3c_mfc_mutex);

	clk_enable(s3c_mfc_hclk);
	clk_enable(s3c_mfc_sclk);
	clk_enable(s3c_mfc_pclk);

	/* 1. MFC Power On(Domain V) */
	mfc_pwr = readl(S3C_NORMAL_CFG);
	mfc_pwr |= (1 << 9);
	__raw_writel(mfc_pwr, S3C_NORMAL_CFG);

	/* 2. Check MFC power on */
	do {
		domain_v_ready = readl(S3C_BLK_PWR_STAT);
		mfc_debug("domain v ready = 0x%X\n", domain_v_ready);
		msleep(1);
	} while (!(domain_v_ready & (1 << 1)));

	/* 3. MFC clock set 133 Mhz */
	if (s3c_mfc_setup_clock() == FALSE)
		return -ENODEV;

	/* 4. Firmware download */
	s3c_mfc_download_boot_firmware();

	/* 
	 * 5. Power On state
	 * Validate all the MFC Instances
	 */
	for (inst_no = 0; inst_no < S3C_MFC_NUM_INSTANCES_MAX; inst_no++) {
		mfcinst_ctx = s3c_mfc_inst_get_context(inst_no);
		if (mfcinst_ctx) {
			is_mfc_on = 1;

	/* 
	 * When MFC Power On, the MFC instance is validated.
	 * Then the MFC operations (DEC_EXE, ENC_EXE, etc.) will be performed again
	 */
			s3c_mfc_inst_pow_on_state(mfcinst_ctx);
			mfc_debug("mfc resume %d-th instance is validated\n", inst_no);
		}
	}

	if (is_mfc_on) {
		/* 5. Restore MFC SFR */
		dwMfcBase = s3c_mfc_sfr_base_virt_addr;
		for (i = S3C_MFC_SAVE_START_ADDR; i <= S3C_MFC_SAVE_END_ADDR; i += 4 ) {
			writel(s3c_mfc_save[index], dwMfcBase + i);
			index++;
		}

		/* 6. Command MFC wakeup */
		s3c_mfc_wakeup();
	}

	mutex_unlock(s3c_mfc_mutex);

	return 0;
}
Esempio n. 26
0
static inline void
lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
{
	__raw_writel(val, fbi->regs + off);
}
Esempio n. 27
0
void iowrite32be(u32 val, void __iomem *addr)
{
	__raw_writel(cpu_to_be32(val), addr);
}
Esempio n. 28
0
static void __init mackerel_init(void)
{
	u32 srcr4;
	struct clk *clk;

	
	clk_set_rate(&sh7372_dv_clki_clk, 27000000);

	sh7372_pinmux_init();

	
	gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
	gpio_request(GPIO_FN_SCIFA0_RXD, NULL);

	
	gpio_request(GPIO_FN_CS5A,	NULL);
	gpio_request(GPIO_FN_IRQ6_39,	NULL);

	
	gpio_request(GPIO_FN_LCDD23,   NULL);
	gpio_request(GPIO_FN_LCDD22,   NULL);
	gpio_request(GPIO_FN_LCDD21,   NULL);
	gpio_request(GPIO_FN_LCDD20,   NULL);
	gpio_request(GPIO_FN_LCDD19,   NULL);
	gpio_request(GPIO_FN_LCDD18,   NULL);
	gpio_request(GPIO_FN_LCDD17,   NULL);
	gpio_request(GPIO_FN_LCDD16,   NULL);
	gpio_request(GPIO_FN_LCDD15,   NULL);
	gpio_request(GPIO_FN_LCDD14,   NULL);
	gpio_request(GPIO_FN_LCDD13,   NULL);
	gpio_request(GPIO_FN_LCDD12,   NULL);
	gpio_request(GPIO_FN_LCDD11,   NULL);
	gpio_request(GPIO_FN_LCDD10,   NULL);
	gpio_request(GPIO_FN_LCDD9,    NULL);
	gpio_request(GPIO_FN_LCDD8,    NULL);
	gpio_request(GPIO_FN_LCDD7,    NULL);
	gpio_request(GPIO_FN_LCDD6,    NULL);
	gpio_request(GPIO_FN_LCDD5,    NULL);
	gpio_request(GPIO_FN_LCDD4,    NULL);
	gpio_request(GPIO_FN_LCDD3,    NULL);
	gpio_request(GPIO_FN_LCDD2,    NULL);
	gpio_request(GPIO_FN_LCDD1,    NULL);
	gpio_request(GPIO_FN_LCDD0,    NULL);
	gpio_request(GPIO_FN_LCDDISP,  NULL);
	gpio_request(GPIO_FN_LCDDCK,   NULL);

	gpio_request(GPIO_PORT31, NULL); 
	gpio_direction_output(GPIO_PORT31, 0); 

	gpio_request(GPIO_PORT151, NULL); 
	gpio_direction_output(GPIO_PORT151, 1);

	
	gpio_request(GPIO_FN_VBUS0_0, NULL);
	gpio_pull_down(GPIO_PORT168CR); 

	
	gpio_request(GPIO_FN_VBUS0_1, NULL);
	gpio_pull_down(GPIO_PORT167CR); 
	gpio_request(GPIO_FN_IDIN_1_113, NULL);

	
	gpio_request(GPIO_FN_FSIAIBT,	NULL);
	gpio_request(GPIO_FN_FSIAILR,	NULL);
	gpio_request(GPIO_FN_FSIAISLD,	NULL);
	gpio_request(GPIO_FN_FSIAOSLD,	NULL);
	gpio_request(GPIO_PORT161,	NULL);
	gpio_direction_output(GPIO_PORT161, 0); 

	gpio_request(GPIO_PORT9,  NULL);
	gpio_request(GPIO_PORT10, NULL);
	gpio_no_direction(GPIO_PORT9CR);  
	gpio_no_direction(GPIO_PORT10CR); 

	intc_set_priority(IRQ_FSI, 3); 

	
	gpio_request(GPIO_FN_FSIBCK, NULL);
	__raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); 

	
	clk = clk_get(NULL, "spu_clk");
	if (!IS_ERR(clk)) {
		clk_set_rate(clk, clk_round_rate(clk, 119600000));
		clk_put(clk);
	}

	
	gpio_request(GPIO_FN_IRQ9_42,	NULL);
	irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);

	
	gpio_request(GPIO_FN_IRQ7_40,	NULL);
	irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);

	
	gpio_request(GPIO_FN_IRQ21,	NULL);
	irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);

	
	gpio_request(GPIO_FN_SDHIWP0, NULL);
	gpio_request(GPIO_FN_SDHICMD0, NULL);
	gpio_request(GPIO_FN_SDHICLK0, NULL);
	gpio_request(GPIO_FN_SDHID0_3, NULL);
	gpio_request(GPIO_FN_SDHID0_2, NULL);
	gpio_request(GPIO_FN_SDHID0_1, NULL);
	gpio_request(GPIO_FN_SDHID0_0, NULL);

#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
	
	gpio_request(GPIO_FN_SDHICMD1, NULL);
	gpio_request(GPIO_FN_SDHICLK1, NULL);
	gpio_request(GPIO_FN_SDHID1_3, NULL);
	gpio_request(GPIO_FN_SDHID1_2, NULL);
	gpio_request(GPIO_FN_SDHID1_1, NULL);
	gpio_request(GPIO_FN_SDHID1_0, NULL);
#endif
	
	gpio_request(GPIO_PORT41, NULL);
	gpio_direction_input(GPIO_PORT41);

	
	gpio_request(GPIO_FN_SDHICMD2, NULL);
	gpio_request(GPIO_FN_SDHICLK2, NULL);
	gpio_request(GPIO_FN_SDHID2_3, NULL);
	gpio_request(GPIO_FN_SDHID2_2, NULL);
	gpio_request(GPIO_FN_SDHID2_1, NULL);
	gpio_request(GPIO_FN_SDHID2_0, NULL);

	
	gpio_request(GPIO_PORT162, NULL);
	gpio_direction_input(GPIO_PORT162);

	
	gpio_request(GPIO_FN_MMCD0_0, NULL);
	gpio_request(GPIO_FN_MMCD0_1, NULL);
	gpio_request(GPIO_FN_MMCD0_2, NULL);
	gpio_request(GPIO_FN_MMCD0_3, NULL);
	gpio_request(GPIO_FN_MMCD0_4, NULL);
	gpio_request(GPIO_FN_MMCD0_5, NULL);
	gpio_request(GPIO_FN_MMCD0_6, NULL);
	gpio_request(GPIO_FN_MMCD0_7, NULL);
	gpio_request(GPIO_FN_MMCCMD0, NULL);
	gpio_request(GPIO_FN_MMCCLK0, NULL);

	
	gpio_request(GPIO_FN_D0_NAF0, NULL);
	gpio_request(GPIO_FN_D1_NAF1, NULL);
	gpio_request(GPIO_FN_D2_NAF2, NULL);
	gpio_request(GPIO_FN_D3_NAF3, NULL);
	gpio_request(GPIO_FN_D4_NAF4, NULL);
	gpio_request(GPIO_FN_D5_NAF5, NULL);
	gpio_request(GPIO_FN_D6_NAF6, NULL);
	gpio_request(GPIO_FN_D7_NAF7, NULL);
	gpio_request(GPIO_FN_D8_NAF8, NULL);
	gpio_request(GPIO_FN_D9_NAF9, NULL);
	gpio_request(GPIO_FN_D10_NAF10, NULL);
	gpio_request(GPIO_FN_D11_NAF11, NULL);
	gpio_request(GPIO_FN_D12_NAF12, NULL);
	gpio_request(GPIO_FN_D13_NAF13, NULL);
	gpio_request(GPIO_FN_D14_NAF14, NULL);
	gpio_request(GPIO_FN_D15_NAF15, NULL);
	gpio_request(GPIO_FN_FCE0, NULL);
	gpio_request(GPIO_FN_WE0_FWE, NULL);
	gpio_request(GPIO_FN_FRB, NULL);
	gpio_request(GPIO_FN_A4_FOE, NULL);
	gpio_request(GPIO_FN_A5_FCDE, NULL);
	gpio_request(GPIO_FN_RD_FSC, NULL);

	
	gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
	gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);

	
	gpio_request(GPIO_FN_VIO_CLK, NULL);
	gpio_request(GPIO_FN_VIO_VD, NULL);
	gpio_request(GPIO_FN_VIO_HD, NULL);
	gpio_request(GPIO_FN_VIO_FIELD, NULL);
	gpio_request(GPIO_FN_VIO_CKO, NULL);
	gpio_request(GPIO_FN_VIO_D7, NULL);
	gpio_request(GPIO_FN_VIO_D6, NULL);
	gpio_request(GPIO_FN_VIO_D5, NULL);
	gpio_request(GPIO_FN_VIO_D4, NULL);
	gpio_request(GPIO_FN_VIO_D3, NULL);
	gpio_request(GPIO_FN_VIO_D2, NULL);
	gpio_request(GPIO_FN_VIO_D1, NULL);
	gpio_request(GPIO_FN_VIO_D0, NULL);

	
	gpio_request(GPIO_FN_HDMI_HPD, NULL);
	gpio_request(GPIO_FN_HDMI_CEC, NULL);

	
	srcr4 = __raw_readl(SRCR4);
	__raw_writel(srcr4 | (1 << 13), SRCR4);
	udelay(50);
	__raw_writel(srcr4 & ~(1 << 13), SRCR4);

	i2c_register_board_info(0, i2c0_devices,
				ARRAY_SIZE(i2c0_devices));
	i2c_register_board_info(1, i2c1_devices,
				ARRAY_SIZE(i2c1_devices));

	sh7372_add_standard_devices();

	platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));

	sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
	sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device);
	sh7372_add_device_to_domain(&sh7372_a4lc, &meram_device);
	sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
	sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device);
	sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device);
	sh7372_add_device_to_domain(&sh7372_a3sp, &nand_flash_device);
	sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
	sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
	sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
#endif
	sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
	sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);

	hdmi_init_pm_clock();
	sh7372_pm_init();
	pm_clk_add(&fsi_device.dev, "spu2");
	pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
}
Esempio n. 29
0
/*
 * Bring one cpu online.
 */
int __init smp_boot_one_cpu(int cpuid)
{
	struct task_struct *idle;
	long timeout;

	/* 
	 * Create an idle task for this CPU.  Note the address wed* give 
	 * to kernel_thread is irrelevant -- it's going to start
	 * where OS_BOOT_RENDEVZ vector in SAL says to start.  But
	 * this gets all the other task-y sort of data structures set
	 * up like we wish.   We need to pull the just created idle task 
	 * off the run queue and stuff it into the init_tasks[] array.  
	 * Sheesh . . .
	 */

	idle = fork_idle(cpuid);
	if (IS_ERR(idle))
		panic("SMP: fork failed for CPU:%d", cpuid);

	idle->thread_info->cpu = cpuid;

	/* Let _start know what logical CPU we're booting
	** (offset into init_tasks[],cpu_data[])
	*/
	cpu_now_booting = cpuid;

	/* 
	** boot strap code needs to know the task address since
	** it also contains the process stack.
	*/
	smp_init_current_idle_task = idle ;
	mb();

	printk("Releasing cpu %d now, hpa=%lx\n", cpuid, cpu_data[cpuid].hpa);

	/*
	** This gets PDC to release the CPU from a very tight loop.
	**
	** From the PA-RISC 2.0 Firmware Architecture Reference Specification:
	** "The MEM_RENDEZ vector specifies the location of OS_RENDEZ which 
	** is executed after receiving the rendezvous signal (an interrupt to 
	** EIR{0}). MEM_RENDEZ is valid only when it is nonzero and the 
	** contents of memory are valid."
	*/
	__raw_writel(IRQ_OFFSET(TIMER_IRQ), cpu_data[cpuid].hpa);
	mb();

	/* 
	 * OK, wait a bit for that CPU to finish staggering about. 
	 * Slave will set a bit when it reaches smp_cpu_init().
	 * Once the "monarch CPU" sees the bit change, it can move on.
	 */
	for (timeout = 0; timeout < 10000; timeout++) {
		if(cpu_online(cpuid)) {
			/* Which implies Slave has started up */
			cpu_now_booting = 0;
			smp_init_current_idle_task = NULL;
			goto alive ;
		}
		udelay(100);
		barrier();
	}

	put_task_struct(idle);
	idle = NULL;

	printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
	return -1;

alive:
	/* Remember the Slave data */
#if (kDEBUG>=100)
	printk(KERN_DEBUG "SMP: CPU:%d came alive after %ld _us\n",
		cpuid, timeout * 100);
#endif /* kDEBUG */
#ifdef ENTRY_SYS_CPUS
	cpu_data[cpuid].state = STATE_RUNNING;
#endif
	return 0;
}
Esempio n. 30
0
static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	__raw_writel(val, mcpdm->io_base + reg);
}