Esempio n. 1
0
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_L1Cache_InvalidateDCacheAll(void) {
  
  /* setup */
  uint32_t orig = __get_SCTLR();
  uint32_t value = 0x0815U;

  L1C_EnableCaches();

  L1C_CleanDCacheAll();

  /* test cached value gets lost */
  
  // WHEN a value is written
  value = 0x4711U;
  
  // ... and the cache is invalidated
  L1C_InvalidateDCacheAll();

  // ... and the cache is disabled
  L1C_DisableCaches();

  // THEN the new value has been lost
  ASSERT_TRUE(value == 0x0815U);
  
  /* tear down */
  L1C_InvalidateDCacheAll();
  __set_SCTLR(orig);
  __ISB();
}
Esempio n. 2
0
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_L1Cache_EnDisable(void) {
  
  uint32_t orig = __get_SCTLR();
  
  L1C_EnableCaches();
  
  uint32_t sctlr = __get_SCTLR();
  ASSERT_TRUE((sctlr  & SCTLR_I_Msk) == SCTLR_I_Msk);
  ASSERT_TRUE((sctlr  & SCTLR_C_Msk) == SCTLR_C_Msk);
  
  L1C_CleanDCacheAll();
  L1C_DisableCaches();
  
  sctlr = __get_SCTLR();
  ASSERT_TRUE((sctlr & SCTLR_I_Msk) == 0U);
  ASSERT_TRUE((sctlr & SCTLR_C_Msk) == 0U);
  
  __set_SCTLR(orig);
  __ISB();
}
Esempio n. 3
0
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_L1Cache_EnDisableBTAC(void) {
  uint32_t orig = __get_SCTLR();
  
  L1C_EnableBTAC();
  
  uint32_t sctlr = __get_SCTLR();
  ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);
  
  L1C_DisableBTAC();
  
  sctlr = __get_SCTLR();
#if __CORTEX_A == 7
  // On Cortex-A7 SCTLR_Z is RAO/WI.
  ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);
#else
  ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == 0U);
#endif

  __set_SCTLR(orig);
  __ISB();
}
Esempio n. 4
0
File: mmu.c Progetto: mabl/ChibiOS
/**
 * @brief   Core/MMU Module initialization.
 * @note    This function is implicitly invoked on system initialization,
 *          there is no need to explicitly initialize the module.
 *
 * @notapi
 */
void __core_init(void) {
  uint32_t pm;

  /*
   * Invalidate L1 D Cache if it was disabled
   */
  pm = __get_SCTLR();
  if ((pm & SCTLR_C_Msk) == 0) {
    __L1C_CleanInvalidateCache(DCISW_INVALIDATE);
  }
  /*
   * Default, undefined regions
   */
  for (pm = 0; pm < 4096; ++pm)
    mmuTable[pm] = TTE_SECT_UNDEF;
  /*
   * ROM region
   *
   * 0x00000000
   */
  mmuTable[0]   = TTE_SECT_SECTION(0x00000000) |
                  TTE_SECT_MEM_NO_CACHEABLE |
                  TTE_SECT_RO_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * NFC SRAM region
   *
   * 0x00100000
   */
  mmuTable[1]   = TTE_SECT_SECTION(0x00100000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * SRAM region
   *
   * 0x00200000
   */
  mmuTable[2]   = TTE_SECT_SECTION(0x00200000) |
                  TTE_SECT_MEM_CACHEABLE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * UDPHS RAM region
   *
   * 0x00300000
   */
  mmuTable[3]   = TTE_SECT_SECTION(0x00300000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * UHPHS region
   *
   * 0x00400000
   */
  mmuTable[4]   = TTE_SECT_SECTION(0x00400000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * UDPHS region
   *
   * 0x00500000
   */
  mmuTable[5]   = TTE_SECT_SECTION(0x00500000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * AXIMX region
   *
   * 0x00600000
   */
  mmuTable[6]   = TTE_SECT_SECTION(0x00600000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * DAP region
   *
   * 0x00700000
   */
  mmuTable[7]   = TTE_SECT_SECTION(0x00700000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * L2CC region, low
   *
   * 0x00a00000
   */
  mmuTable[0xa] = TTE_SECT_SECTION(0x00a00000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * L2CC region, hi
   *
   * 0x00b00000
   */
  mmuTable[0xb] = TTE_SECT_SECTION(0x00b00000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * EBI regions
   *
   * 0x10000000 - 0x1fffffff
   */
  for (pm = 0x100; pm < 0x200; pm++)
    mmuTable[pm] =  TTE_SECT_SECTION(pm << 20) |
                    TTE_SECT_MEM_STRONGLY_ORD |
                    TTE_SECT_RW_ACCESS |
                    TTE_SECT_DOM(0x0F) |
                    TTE_SECT_EXE_NEVER |
                    TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * DDR regions
   *
   * 0x20000000 - 0x3fffffff
   */
  for (pm = 0x200; pm < 0x400; pm++)
    mmuTable[pm] =  TTE_SECT_SECTION(pm << 20) |
                    TTE_SECT_MEM_CACHEABLE |
                    TTE_SECT_RW_ACCESS |
                    TTE_SECT_DOM(0x0F) |
                    TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * DDR AESB regions
   *
   * 0x40000000 - 0x5fffffff
   */
  for (pm = 0x400; pm < 0x600; pm++)
    mmuTable[pm] =  TTE_SECT_SECTION(pm << 20) |
                    TTE_SECT_MEM_CACHEABLE |
                    TTE_SECT_RW_ACCESS |
                    TTE_SECT_DOM(0x0F) |
                    TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * EBI 1, 2 and 3 regions
   *
   * 0x60000000 - 0x8fffffff
   */
  for (pm = 0x600; pm < 0x900; pm++)
    mmuTable[pm] =  TTE_SECT_SECTION(pm << 20) |
                    TTE_SECT_MEM_STRONGLY_ORD |
                    TTE_SECT_RW_ACCESS |
                    TTE_SECT_DOM(0x0F) |
                    TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * QSPI0/1 AESB MEM regions
   *
   * 0x90000000 - 0x9fffffff
   */
  for (pm = 0x900; pm < 0xa00; pm++)
    mmuTable[pm] =  TTE_SECT_SECTION(pm << 20) |
                    TTE_SECT_MEM_STRONGLY_ORD |
                    TTE_SECT_RW_ACCESS |
                    TTE_SECT_DOM(0x0F) |
                    TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * SDMMC0/1 regions
   *
   * 0xa0000000 - 0xbfffffff
   */
  for (pm = 0xa00; pm < 0xc00; pm++)
    mmuTable[pm] =  TTE_SECT_SECTION(pm << 20) |
                    TTE_SECT_MEM_STRONGLY_ORD |
                    TTE_SECT_RW_ACCESS |
                    TTE_SECT_DOM(0x0F) |
                    TTE_SECT_EXE_NEVER |
                    TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * NFC regions
   *
   * 0xc0000000 - 0xcfffffff
   */
  for (pm = 0xc00; pm < 0xd00; pm++)
    mmuTable[pm] =  TTE_SECT_SECTION(pm << 20) |
                    TTE_SECT_MEM_STRONGLY_ORD |
                    TTE_SECT_RW_ACCESS |
                    TTE_SECT_DOM(0x0F) |
                    TTE_SECT_EXE_NEVER |
                    TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * QSPI0/1 MEM regions
   *
   * 0xd0000000 - 0xdfffffff
   */
  for (pm = 0xd00; pm < 0xe00; pm++)
    mmuTable[pm] =  TTE_SECT_SECTION(pm << 20) |
                    TTE_SECT_MEM_STRONGLY_ORD |
                    TTE_SECT_RW_ACCESS |
                    TTE_SECT_DOM(0x0F) |
                    TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * Internal peripherals regions
   *
   * 0xf0000000
   * 0xf8000000
   * 0xfc000000
   */
  mmuTable[0xf00] = TTE_SECT_SECTION(0xf0000000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  mmuTable[0xf80] = TTE_SECT_SECTION(0xf8000000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  mmuTable[0xfc0] = TTE_SECT_SECTION(0xfc000000) |
                  TTE_SECT_DEVICE |
                  TTE_SECT_RW_ACCESS |
                  TTE_SECT_DOM(0x0F) |
                  TTE_SECT_EXE_NEVER |
                  TTE_SECT_S | TTE_TYPE_SECT;
  /*
   * Invalidate TLB and L1 I cache
   * Enable caches and MMU
   */
  MMU_InvalidateTLB();
  __set_TTBR0((uint32_t)mmuTable|0x5B);
  __set_DACR(0xC0000000);
  __DSB();
  __ISB();

  /*
   * L1 I cache invalidate and enable
   */
  pm = __get_SCTLR();
  if ((pm & SCTLR_I_Msk) == 0) {
    __set_ICIALLU(0);
    __set_SCTLR(pm | SCTLR_I_Msk);
  }
  /*
   * MMU enable
   */
  pm = __get_SCTLR();
  if ((pm & SCTLR_M_Msk) == 0)
    __set_SCTLR(pm | SCTLR_M_Msk);
  /*
   * L1 D cache enable
   */
  pm = __get_SCTLR();
  if ((pm & SCTLR_C_Msk) == 0) {
    __set_SCTLR(pm | SCTLR_C_Msk);
  }
}