static inline void cpu_leave_lowpower(unsigned int cpu)
{
//HOTPLUG_INFO("cpu_leave_lowpower\n");
if (((cpu == 4) && (cpu_online(5) == 0) && (cpu_online(6) == 0) && (cpu_online(7) == 0)) ||
((cpu == 5) && (cpu_online(4) == 0) && (cpu_online(6) == 0) && (cpu_online(7) == 0)) ||
((cpu == 6) && (cpu_online(4) == 0) && (cpu_online(5) == 0) && (cpu_online(7) == 0)) ||
((cpu == 7) && (cpu_online(4) == 0) && (cpu_online(5) == 0) && (cpu_online(6) == 0)))
{
/* Enable CA15L snoop function */
#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
mcusys_smc_write_phy(virt_to_phys(MP1_AXI_CONFIG), REG_READ(MP1_AXI_CONFIG) & ~ACINACTM);
#else //#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
mcusys_smc_write(MP1_AXI_CONFIG, REG_READ(MP1_AXI_CONFIG) & ~ACINACTM);
#endif //#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
/* Enable snoop requests and DVM message requests */
REG_WRITE(CCI400_SI3_SNOOP_CONTROL, REG_READ(CCI400_SI3_SNOOP_CONTROL) | (SNOOP_REQ | DVM_MSG_REQ));
while (REG_READ(CCI400_STATUS) & CHANGE_PENDING);
}
/* Set the ACTLR.SMP bit to 1 for SMP mode */
__switch_to_smp();
/* Enable dcache */
__enable_dcache();
}
static inline void cpu_leave_lowpower(unsigned int cpu)
{
//HOTPLUG_INFO("cpu_leave_lowpower\n");
/* Set the ACTLR.SMP bit to 1 for SMP mode */
__switch_to_smp();
/* Enable dcache */
__enable_dcache();
}
static inline void cpu_leave_lowpower(unsigned int cpu)
{
/* HOTPLUG_INFO("cpu_leave_lowpower\n"); */
if ((cpu == 3 && cpu_online(2) == 0) || (cpu == 2 && cpu_online(3) == 0)) {
spm_write(CA15_MISC_DBG, spm_read(CA15_MISC_DBG) & ~0x11);
spm_write(CA15_CCI400_DVM_EN, spm_read(CA15_CCI400_DVM_EN) | 0x3);
/* wait cci change pending */
while (spm_read(CCI400_STATUS) & 0x1)
;
}
/* Set the ACTLR.SMP bit to 1 for SMP mode */
__switch_to_smp();
/* Enable dcache */
__enable_dcache();
}
