void write_eeprom16(uint8_t *buf) { int i; for(i=0;i<(SIZE_EEPROM_16/EEPROM_BLOCK_SIZE);i++) { eeprom_write(i,buf+(i*EEPROM_BLOCK_SIZE)); __wait_ms(15); } }
static void dll_switch_to_enable_mode(u32 clk_emc_div) { u32 dpll_freq; u32 clk_emc_freq; volatile u32 i; u32 value; u32 value_temp; //for(i =0 ; i < 0x80000000; i++); dpll_freq = get_dpll_freq_value(); //check clk emc not less thans 100MHz switch(dpll_freq) { case 400: if(clk_emc_div > 3) { while(1); } break; case 200: if(clk_emc_div > 1) { while(1); } break; case 100: if(clk_emc_div > 0) { while(1); } break; } REG32(SPRD_UART1_BASE) = '0'; __wait_ms(5); //modify_reg_field(PUBL_REG_BASE + PUBL_CFG_ADD_DSGCR, 3, 1, 0x0);//clear LPI0RD REG32(PUBL_REG_BASE + PUBL_CFG_ADD_DSGCR) &= ~(1 << 3); REG32(SPRD_UART1_BASE) = '1'; move_upctl_state_to_low_power(); //uart_trace("2", 1); REG32(SPRD_UART1_BASE) = '2'; #if 0 value_temp = REG32(UMCTL_REG_BASE+UMCTL_CFG_ADD_STAT) ; //uart_trace((value_temp&0xff) + '0', 1); REG32(SPRD_UART1_BASE) = '3'; #endif __wait_ms(5); //for(i = 0; i < 0x1000000; i++); if(1) { disable_clk_emc(); __wait_ms(5); REG32(SPRD_UART1_BASE) = '3'; if(0) { //can only do when memory in seldf refresh mode //publ_do_zq_calibration(); } enable_ddrphy_dll(); //uart_trace("3", 1); __wait_ms(5); wait_n_pclk_cycle(4);//null read to wait 100ns per DLL reuirement assert_reset_ddrphy_dll(); REG32(SPRD_UART1_BASE) = '4'; //uart_trace("4", 1); __wait_ms(5); wait_n_pclk_cycle(2); modify_clk_emc_div(clk_emc_div);//update clk_emc req //uart_trace("5", 1); __wait_ms(5); enable_clk_emc(); //uart_trace("6", 1); wait_n_pclk_cycle(2);//let clk_emc toggle for some time before reset is released deassert_reset_ddrphy_dll(); //uart_trace("7", 1); } if(0){ wait_n_pclk_cycle(100 * 1000 / 25); } else { polling_reg_bit_field(PUBL_REG_BASE + PUBL_CFG_ADD_PGSR, 0, 1, 1); REG32(SPRD_UART1_BASE) = '9'; __wait_ms(10); //step 4 //DLL need 5.12us to lock REG32(PUBL_REG_BASE + PUBL_CFG_ADD_PIR) = 0x5; wait_n_pclk_cycle(5); polling_reg_bit_field(PUBL_REG_BASE + PUBL_CFG_ADD_PGSR, 0, 1, 1); REG32(SPRD_UART1_BASE) = 'a'; __wait_ms(10); } //if(0) { //} //else { // // //} //modify_reg_field(PUBL_REG_BASE + PUBL_CFG_ADD_DSGCR, 3, 1, 0x1);//set LPI0PD REG32(PUBL_REG_BASE + PUBL_CFG_ADD_DSGCR) |= (1 << 3); //REG32(SPRD_UART1_BASE) = 'b'; //__wait_ms(20); //move_upctl_state_to_low_power(); //REG32(UMCTL_REG_BASE+UMCTL_CFG_ADD_SCTL) = 0x1; //__wait_ms(20); value_temp = REG32(UMCTL_REG_BASE+UMCTL_CFG_ADD_STAT) ; #if 0 value = REG32(SPRD_GPIO_BASE + 0x480); value &= ~(1 << 15); REG32(SPRD_GPIO_BASE + 0x480) = value; __wait_ms(2); value |= (1 << 15); REG32(SPRD_GPIO_BASE + 0x480) = value; #endif move_upctl_state_to_access(); //uart_trace("9", 1); REG32(SPRD_UART1_BASE) = '9'; //__wait_ms(80); // REG32(SPRD_UART1_BASE) = 'c'; //for(i = 0; i < 0x1000000; i++); }
static void dll_switch_to_disable_mode(u32 clk_emc_div) { u32 dpll_freq; u32 bps200; volatile u32 i; REG32(SPRD_UART1_BASE) = '6'; dpll_freq = get_dpll_freq_value(); switch(dpll_freq) { case 400: if(clk_emc_div >= 3) { bps200 = 0; } else { bps200 = 1; } break; case 200: if(clk_emc_div >= 1) { bps200 = 0; } else { bps200 = 1; } break; case 100: bps200 = 0; break; default: while(1); } if((clk_emc_div == 0) && (dpll_freq > 200)) { while(1); } REG32(SPRD_UART1_BASE) = '0'; __wait_ms(5); move_upctl_state_to_low_power(); REG32(SPRD_UART1_BASE) = '1'; __wait_ms(5);; disable_clk_emc(); REG32(SPRD_UART1_BASE) = '2'; __wait_ms(5); set_ddrphy_dll_bps200_mode(bps200); REG32(SPRD_UART1_BASE) = '3'; __wait_ms(5); disable_ddrphy_dll(); REG32(SPRD_UART1_BASE) = '4'; __wait_ms(5); modify_clk_emc_div(clk_emc_div);//update clk_emc freq REG32(SPRD_UART1_BASE) = '5'; __wait_ms(5); enable_clk_emc(); REG32(SPRD_UART1_BASE) = '6'; __wait_ms(5); //for(i = 0; i < 10; i++); move_upctl_state_to_access(); REG32(SPRD_UART1_BASE) = '7'; __wait_ms(5); }