static void nouveau_disk_cache_create(struct nouveau_screen *screen) { struct mesa_sha1 ctx; unsigned char sha1[20]; char cache_id[20 * 2 + 1]; uint64_t driver_flags = 0; _mesa_sha1_init(&ctx); if (!disk_cache_get_function_identifier(nouveau_disk_cache_create, &ctx)) return; _mesa_sha1_final(&ctx, sha1); disk_cache_format_hex_id(cache_id, sha1, 20 * 2); if (screen->prefer_nir) driver_flags |= NOUVEAU_SHADER_CACHE_FLAGS_IR_NIR; else driver_flags |= NOUVEAU_SHADER_CACHE_FLAGS_IR_TGSI; screen->disk_shader_cache = disk_cache_create(nouveau_screen_get_name(&screen->base), cache_id, driver_flags); }
void tu_hash_shaders(unsigned char *hash, const VkPipelineShaderStageCreateInfo **stages, const struct tu_pipeline_layout *layout, const struct tu_pipeline_key *key, uint32_t flags) { struct mesa_sha1 ctx; _mesa_sha1_init(&ctx); if (key) _mesa_sha1_update(&ctx, key, sizeof(*key)); if (layout) _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1)); for (int i = 0; i < MESA_SHADER_STAGES; ++i) { if (stages[i]) { TU_FROM_HANDLE(tu_shader_module, module, stages[i]->module); const VkSpecializationInfo *spec_info = stages[i]->pSpecializationInfo; _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1)); _mesa_sha1_update(&ctx, stages[i]->pName, strlen(stages[i]->pName)); if (spec_info) { _mesa_sha1_update( &ctx, spec_info->pMapEntries, spec_info->mapEntryCount * sizeof spec_info->pMapEntries[0]); _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize); } } } _mesa_sha1_update(&ctx, &flags, 4); _mesa_sha1_final(&ctx, hash); }
void _mesa_sha1_compute(const void *data, size_t size, unsigned char result[20]) { struct mesa_sha1 *ctx; ctx = _mesa_sha1_init(); _mesa_sha1_update(ctx, data, size); _mesa_sha1_final(ctx, result); }
VkResult radv_CreatePipelineLayout( VkDevice _device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout) { RADV_FROM_HANDLE(radv_device, device, _device); struct radv_pipeline_layout *layout; struct mesa_sha1 ctx; assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO); layout = vk_alloc2(&device->alloc, pAllocator, sizeof(*layout), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (layout == NULL) return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); layout->num_sets = pCreateInfo->setLayoutCount; unsigned dynamic_offset_count = 0; _mesa_sha1_init(&ctx); for (uint32_t set = 0; set < pCreateInfo->setLayoutCount; set++) { RADV_FROM_HANDLE(radv_descriptor_set_layout, set_layout, pCreateInfo->pSetLayouts[set]); layout->set[set].layout = set_layout; layout->set[set].dynamic_offset_start = dynamic_offset_count; for (uint32_t b = 0; b < set_layout->binding_count; b++) { dynamic_offset_count += set_layout->binding[b].array_size * set_layout->binding[b].dynamic_offset_count; if (set_layout->binding[b].immutable_samplers_offset) _mesa_sha1_update(&ctx, radv_immutable_samplers(set_layout, set_layout->binding + b), set_layout->binding[b].array_size * 4 * sizeof(uint32_t)); } _mesa_sha1_update(&ctx, set_layout->binding, sizeof(set_layout->binding[0]) * set_layout->binding_count); } layout->dynamic_offset_count = dynamic_offset_count; layout->push_constant_size = 0; for (unsigned i = 0; i < pCreateInfo->pushConstantRangeCount; ++i) { const VkPushConstantRange *range = pCreateInfo->pPushConstantRanges + i; layout->push_constant_size = MAX2(layout->push_constant_size, range->offset + range->size); } layout->push_constant_size = align(layout->push_constant_size, 16); _mesa_sha1_update(&ctx, &layout->push_constant_size, sizeof(layout->push_constant_size)); _mesa_sha1_final(&ctx, layout->sha1); *pPipelineLayout = radv_pipeline_layout_to_handle(layout); return VK_SUCCESS; }
static void si_disk_cache_create(struct si_screen *sscreen) { /* Don't use the cache if shader dumping is enabled. */ if (sscreen->debug_flags & DBG_ALL_SHADERS) return; struct mesa_sha1 ctx; unsigned char sha1[20]; char cache_id[20 * 2 + 1]; _mesa_sha1_init(&ctx); if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) || !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx)) return; _mesa_sha1_final(&ctx, sha1); disk_cache_format_hex_id(cache_id, sha1, 20 * 2); /* These flags affect shader compilation. */ #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \ DBG(SI_SCHED) | \ DBG(GISEL) | \ DBG(UNSAFE_MATH)) uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS; /* Add the high bits of 32-bit addresses, which affects * how 32-bit addresses are expanded to 64 bits. */ STATIC_ASSERT(ALL_FLAGS <= UINT_MAX); assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi); shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32; if (sscreen->options.enable_nir) shader_debug_flags |= 1ull << 48; sscreen->disk_shader_cache = disk_cache_create(sscreen->info.name, cache_id, shader_debug_flags); }