/**
* @b Description
* @n
* The function is invoked by the SRIO Driver to indicate that a
* descriptor is finished being accessed.
*
* @param[in] drvHandle
* Driver Instance for which descriptor is being accessed.
* @param[in] ptr
* Pointer to the descriptor being accessed
* @param[in] size
* Size of the descriptor (Only valid for Driver Managed)
*
* @retval
* None
*/
void Osal_srioEndDescriptorAccess (Srio_DrvHandle drvHandle, void* ptr, uint32_t descSize)
{
/* In the Application the descriptors are located in Core 0 Global address space
* If they are accessed from other cores we need to ensure that there is an MFENCE so
* that all the access to the descriptors are complete before we start pushing them
* out. */
_mfence();
}
/**
* @b Description
* @n
* The function is used by the SRIO driver to indicate that its
* ending access to a block of memory. We need to ensure that the
* contents of the cache are written back to the actual memory.
*
* @param[in] ptr
* Pointer to the buffer
* @param[in] size
* Size of the buffer
*
* @retval
* None
*/
void Osal_srioEndMemAccess(void* ptr, uint32_t size)
{
#if 0
CACHE_wbL1d (ptr, size, CACHE_WAIT);
_mfence();
#else
UInt key;
/* Disable Interrupts */
key = Hwi_disable();
/* Writeback the cache. */
CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
/* Reenable Interrupts. */
Hwi_restore(key);
#endif
}
/**
* @b Description
* @n
* The function is used to indicate that the block of memory has
* finished being accessed. If the memory block is cached then the
* application would need to ensure that the contents of the cache
* are updated immediately to the actual memory.
*
* @param[in] ptr
* Address of memory block
* @param[in] size
* Size of memory block
*
* @retval
* Not Applicable
*/
void Osal_qmssEndMemAccess (void *ptr, uint32_t size)
{
#if 0
/* Writeback L1D cache and wait until operation is complete.
* Use this approach if L2 cache is not enabled */
CACHE_wbL1d (ptr, size, CACHE_WAIT);
_mfence();
#else
UInt key;
/* Disable Interrupts */
key = Hwi_disable();
/* Writeback the contents of the cache. */
CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
/* Reenable Interrupts. */
Hwi_restore(key);
#endif
}
/******************************************************************************
* flushCache
******************************************************************************/
static void flushCache (void)
{
uint32_t key;
/* Disable Interrupts */
key = _disable_interrupts();
CSL_XMC_invalidatePrefetchBuffer();
/*-------------------------------------------------------------------------
* Also flushes L1P and L1D.
*------------------------------------------------------------------------*/
CACHE_wbInvAllL2(CACHE_NOWAIT);
_mfence();
asm(" NOP 9");
asm(" NOP 7");
/* Reenable Interrupts. */
_restore_interrupts(key);
}