static inline void hieth_clk_dis(void)
{
unsigned int val;
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val &= ~(1 << 8);
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
}
static inline void hieth_clk_dis(void)
{
ulong val;
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val &= ~ETH_CLK_ENABLE;
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
}
static inline void hieth_clk_ena(void)
{
unsigned int val;
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val |= (1 << 1);
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
}
static void hieth_set_regbit(unsigned long addr, int bit, int shift)
{
unsigned long reg;
reg = _readl(addr);
bit = bit ? 1 : 0;
reg &= ~(1 << shift);
reg |= bit << shift;
_writel(reg, addr);
}
static void hieth_set_regbit(ulong reg, int bit, int shift)
{
ulong val;
val = _readl(reg);
bit = bit ? 1 : 0;
val &= ~(1<<shift);
val |= bit<<shift;
_writel(val, reg);
}
static void hieth_phy_reset(void)
{
#ifdef INNER_PHY
ulong rst;
rst = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
rst |= ETH_PHY_RESET;
_writel(rst, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
/* udelay at least 10ms */
udelay(15000);
rst = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
rst &= ~ETH_PHY_RESET;
_writel(rst, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
#endif
#ifdef HISFV_RESET_GPIO_EN
unsigned int val;
/*gpiox[x] set to reset, then delay 200ms*/
val = __raw_readw(HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
val |= (HISFV_RESET_GPIO_DIR_OUT << HISFV_RESET_GPIO_BIT);
__raw_writew(val, HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
__raw_writew(HISFV_RESET_GPIO_DATA,
HISFV_RESET_GPIO_BASE + (4 << HISFV_RESET_GPIO_BIT));
udelay(200000);
/*then,cancel reset,and should delay 200ms*/
val = __raw_readw(HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
val |= (HISFV_RESET_GPIO_DIR_OUT << HISFV_RESET_GPIO_BIT);
__raw_writew(val, HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
__raw_writew(((!HISFV_RESET_GPIO_DATA) << HISFV_RESET_GPIO_BIT),
HISFV_RESET_GPIO_BASE + (4 << HISFV_RESET_GPIO_BIT));
udelay(20000);
#endif
}
static void hieth_internal_phy_reset(void)
{
unsigned int val;
val = _readl(HIETH_FEPHY_SELECT);
/* if not use fephy, leave it's clk disabled */
if ((val & (1 << 8)) != 0)
return;
/* LDO output 1.1V */
_writel(0x68, HIETH_FEPHY_LDO_CTRL);
/* FEPHY enable clock */
val = _readl(HIETH_SYSREG_BASE + HIETHPHY_SYSREG_REG);
val |= (1);
_writel(val, HIETH_SYSREG_BASE + HIETHPHY_SYSREG_REG);
/* set FEPHY address */
val = _readl(INTERNAL_FEPHY_ADDR);
val &= ~(0x1F);
val |= (U_PHY_ADDR & 0x1F);
_writel(val, INTERNAL_FEPHY_ADDR);
/* FEPHY set reset */
val = _readl(HIETH_SYSREG_BASE + HIETHPHY_SYSREG_REG);
val |= (1 << 4);
_writel(val, HIETH_SYSREG_BASE + HIETHPHY_SYSREG_REG);
udelay(10);
/* FEPHY cancel reset */
val = _readl(HIETH_SYSREG_BASE + HIETHPHY_SYSREG_REG);
val &= ~(1 << 4);
_writel(val, HIETH_SYSREG_BASE + HIETHPHY_SYSREG_REG);
udelay(20000);
}
void hieth_sys_init(void)
{
SFE_OFF;
#if 0
/* enable mdio clk */
unsigned int val = _readl(HIETH_SYSREG_BASE + ETH_X5V100_MDIO_CLK_EN);
_writel(val | (1<<26), HIETH_SYSREG_BASE + ETH_X5V100_MDIO_CLK_EN);
#endif
#ifdef HISFV_RESET_GPIO_EN
unsigned int val = 0;
/*gpiox[x] reset*/
/*first reset,then delay 200ms*/
val = __raw_readw(HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
val |= (HISFV_RESET_GPIO_DIR_OUT << HISFV_RESET_GPIO_BIT);
__raw_writew(val,HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
__raw_writew(HISFV_RESET_GPIO_DATA, HISFV_RESET_GPIO_BASE + (4 << HISFV_RESET_GPIO_BIT));
udelay(200000);
/*then,cancel reset,and should delay 200ms*/
val = __raw_readw(HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
val |= (HISFV_RESET_GPIO_DIR_OUT << HISFV_RESET_GPIO_BIT);
__raw_writew(val,HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
__raw_writew(((!HISFV_RESET_GPIO_DATA) << HISFV_RESET_GPIO_BIT), HISFV_RESET_GPIO_BASE + (4 << HISFV_RESET_GPIO_BIT));
udelay(20000);
#endif
// function_sel = _readl(HIETH_SYSREG_BASE + REG_FUNC_SEL);
// hieth_reset(1);
// hieth_function_sel(0, 1);
hieth_clk_ena();
hieth_reset(0);
SFL;
}
static void hieth_phy_reset(void)
{
long long chipid;
unsigned int val;
unsigned int old;
chipid = get_chipid();
if (_HI3712_V100 == chipid) {
/* TODO: HI3712 ASIC should config GPIO for phy reset!!. */
/* config pin re-use to miirst */
old = val = _readl(HI3712_ETH_GPIO_BASE + HI3712_ETH_GPIO_REG);
val |= 0x1;
_writel(val, HI3712_ETH_GPIO_BASE + HI3712_ETH_GPIO_REG);
/* do phy reset */
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val |= HI3712_ETH_SYSREG_RST_BIT;
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
udelay(20000);
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val &= ~HI3712_ETH_SYSREG_RST_BIT;
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
udelay(20000);
_writel(old, HI3712_ETH_GPIO_BASE + HI3712_ETH_GPIO_REG);
} else if (chipid == _HI3716M_V300) {
/* config pin re-use to miirst */
old = val =
_readl(HI3716MV300_ETH_GPIO_BASE +
HI3716MV300_ETH_GPIO_REG);
val |= 0x1;
_writel(val,
HI3716MV300_ETH_GPIO_BASE + HI3716MV300_ETH_GPIO_REG);
/* do phy reset */
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val |= HI3716MV300_ETH_SYSREG_RST_BIT;
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
udelay(20000);
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val &= ~HI3716MV300_ETH_SYSREG_RST_BIT;
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
udelay(20000);
_writel(old,
HI3716MV300_ETH_GPIO_BASE + HI3716MV300_ETH_GPIO_REG);
} else {
# ifdef HISFV_RESET_GPIO_EN
/* gpiox[x] set to reset, then delay 200ms */
val = __raw_readb(HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
val |= (HISFV_RESET_GPIO_DIR_OUT << HISFV_RESET_GPIO_BIT);
__raw_writeb(val, HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
__raw_writeb(HISFV_RESET_GPIO_DATA,
HISFV_RESET_GPIO_BASE +
(4 << HISFV_RESET_GPIO_BIT));
udelay(200000);
/* then,cancel reset,and should delay 200ms */
val = __raw_readb(HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
val |= (HISFV_RESET_GPIO_DIR_OUT << HISFV_RESET_GPIO_BIT);
__raw_writeb(val, HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
__raw_writeb(((!HISFV_RESET_GPIO_DATA) << HISFV_RESET_GPIO_BIT),
HISFV_RESET_GPIO_BASE +
(4 << HISFV_RESET_GPIO_BIT));
udelay(20000);
# endif
}
}
