bool radv_init_llvm_compiler(struct ac_llvm_compiler *info,
bool okay_to_leak_target_library_info,
bool thread_compiler,
enum radeon_family family,
enum ac_target_machine_options tm_options)
{
if (thread_compiler) {
for (auto &I : radv_llvm_per_thread_list) {
if (I.is_same(family, tm_options)) {
*info = I.llvm_info;
return true;
}
}
radv_llvm_per_thread_list.emplace_back(family, tm_options);
radv_llvm_per_thread_info &tinfo = radv_llvm_per_thread_list.back();
if (!tinfo.init()) {
radv_llvm_per_thread_list.pop_back();
return false;
}
*info = tinfo.llvm_info;
return true;
}
if (!ac_init_llvm_compiler(info,
okay_to_leak_target_library_info,
family,
tm_options))
return false;
return true;
}
bool init(void)
{
if (!ac_init_llvm_compiler(&llvm_info,
true,
family,
tm_options))
return false;
passes = ac_create_llvm_passes(llvm_info.tm);
if (!passes)
return false;
return true;
}
static void si_init_compiler(struct si_screen *sscreen,
struct ac_llvm_compiler *compiler)
{
/* Only create the less-optimizing version of the compiler on APUs
* predating Ryzen (Raven). */
bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
sscreen->info.chip_class <= VI;
enum ac_target_machine_options tm_options =
(sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
(sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
(sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
(sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
(!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
(sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
(create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
ac_init_llvm_once();
ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
compiler->passes = ac_create_llvm_passes(compiler->tm);
if (compiler->low_opt_tm)
compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
}
