static int __init acpuclk_9625_probe(struct platform_device *pdev)
{
struct resource *res;
u32 regval, i;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rcg_base");
if (!res)
return -EINVAL;
drv_data.apcs_rcg_config = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!drv_data.apcs_rcg_config)
return -ENOMEM;
drv_data.apcs_rcg_cmd = drv_data.apcs_rcg_config;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwr_base");
if (!res)
return -EINVAL;
drv_data.apcs_cpu_pwr_ctl = ioremap(res->start, resource_size(res));
if (!drv_data.apcs_cpu_pwr_ctl)
return -ENOMEM;
drv_data.vdd_cpu = devm_regulator_get(&pdev->dev, "a5_cpu");
if (IS_ERR(drv_data.vdd_cpu)) {
dev_err(&pdev->dev, "regulator for %s get failed\n", "a5_cpu");
return PTR_ERR(drv_data.vdd_cpu);
}
drv_data.vdd_mem = devm_regulator_get(&pdev->dev, "a5_mem");
if (IS_ERR(drv_data.vdd_mem)) {
dev_err(&pdev->dev, "regulator for %s get failed\n", "a5_mem");
return PTR_ERR(drv_data.vdd_mem);
}
for (i = 0; i < NUM_SRC; i++) {
if (!drv_data.src_clocks[i].name)
continue;
drv_data.src_clocks[i].clk =
devm_clk_get(&pdev->dev, drv_data.src_clocks[i].name);
if (IS_ERR(drv_data.src_clocks[i].clk)) {
dev_err(&pdev->dev, "Unable to get clock %s\n",
drv_data.src_clocks[i].name);
return -EPROBE_DEFER;
}
}
/* Disable hardware gating of gpll0 to A5SS */
regval = readl_relaxed(drv_data.apcs_cpu_pwr_ctl);
regval |= GPLL0_TO_A5_ALWAYS_ENABLE;
writel_relaxed(regval, drv_data.apcs_cpu_pwr_ctl);
clk_prepare_enable(drv_data.src_clocks[PLL0].clk);
return acpuclk_cortex_init(pdev, &drv_data);
}
static int __init acpuclk_a7_probe(struct platform_device *pdev)
{
struct resource *res;
u32 i;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rcg_base");
if (!res)
return -EINVAL;
drv_data.apcs_rcg_cmd = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!drv_data.apcs_rcg_cmd)
return -ENOMEM;
drv_data.apcs_rcg_config = drv_data.apcs_rcg_cmd + 4;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pte_efuse");
if (res) {
drv_data.pte_efuse_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!drv_data.pte_efuse_base)
return -ENOMEM;
}
drv_data.vdd_cpu = devm_regulator_get(&pdev->dev, "a7_cpu");
if (IS_ERR(drv_data.vdd_cpu)) {
dev_err(&pdev->dev, "regulator for %s get failed\n", "a7_cpu");
return PTR_ERR(drv_data.vdd_cpu);
}
for (i = 0; i < NUM_SRC; i++) {
if (!drv_data.src_clocks[i].name)
continue;
drv_data.src_clocks[i].clk =
devm_clk_get(&pdev->dev, drv_data.src_clocks[i].name);
if (IS_ERR(drv_data.src_clocks[i].clk)) {
dev_err(&pdev->dev, "Unable to get clock %s\n",
drv_data.src_clocks[i].name);
return -EPROBE_DEFER;
}
}
/* Enable the always on source */
clk_prepare_enable(drv_data.src_clocks[PLL0].clk);
return acpuclk_cortex_init(pdev, &drv_data);
}
