void gendmultu(usf_state_t * state) { #ifdef INTERPRET_DMULTU gencallinterp(state, (unsigned int)state->current_instruction_table.DMULTU, 0); #else free_all_registers(state); simplify_access(state); mov_eax_memoffs32(state, (unsigned int *)state->dst->f.r.rs); mul_m32(state, (unsigned int *)state->dst->f.r.rt); // EDX:EAX = temp1 mov_memoffs32_eax(state, (unsigned int *)(&state->lo)); mov_reg32_reg32(state, EBX, EDX); // EBX = temp1>>32 mov_eax_memoffs32(state, (unsigned int *)state->dst->f.r.rs); mul_m32(state, (unsigned int *)(state->dst->f.r.rt)+1); add_reg32_reg32(state, EBX, EAX); adc_reg32_imm32(state, EDX, 0); mov_reg32_reg32(state, ECX, EDX); // ECX:EBX = temp2 mov_eax_memoffs32(state, (unsigned int *)(state->dst->f.r.rs)+1); mul_m32(state, (unsigned int *)state->dst->f.r.rt); // EDX:EAX = temp3 add_reg32_reg32(state, EBX, EAX); adc_reg32_imm32(state, ECX, 0); // ECX:EBX = result2 mov_m32_reg32(state, (unsigned int*)(&state->lo)+1, EBX); mov_reg32_reg32(state, EDI, EDX); // EDI = temp3>>32 mov_eax_memoffs32(state, (unsigned int *)(state->dst->f.r.rs)+1); mul_m32(state, (unsigned int *)(state->dst->f.r.rt)+1); add_reg32_reg32(state, EAX, EDI); adc_reg32_imm32(state, EDX, 0); // EDX:EAX = temp4 add_reg32_reg32(state, EAX, ECX); adc_reg32_imm32(state, EDX, 0); // EDX:EAX = result3 mov_memoffs32_eax(state,(unsigned int *)(&state->hi)); mov_m32_reg32(state, (unsigned int *)(&state->hi)+1, EDX); #endif }
void gendmultu() { #ifdef INTERPRET_DMULTU gencallinterp((unsigned long)DMULTU, 0); #else free_all_registers(); simplify_access(); mov_eax_memoffs32((unsigned long *)dst->f.r.rs); mul_m32((unsigned long *)dst->f.r.rt); // EDX:EAX = temp1 mov_memoffs32_eax((unsigned long *)(&lo)); mov_reg32_reg32(EBX, EDX); // EBX = temp1>>32 mov_eax_memoffs32((unsigned long *)dst->f.r.rs); mul_m32((unsigned long *)(dst->f.r.rt)+1); add_reg32_reg32(EBX, EAX); adc_reg32_imm32(EDX, 0); mov_reg32_reg32(ECX, EDX); // ECX:EBX = temp2 mov_eax_memoffs32((unsigned long *)(dst->f.r.rs)+1); mul_m32((unsigned long *)dst->f.r.rt); // EDX:EAX = temp3 add_reg32_reg32(EBX, EAX); adc_reg32_imm32(ECX, 0); // ECX:EBX = result2 mov_m32_reg32((unsigned long*)(&lo)+1, EBX); mov_reg32_reg32(ESI, EDX); // ESI = temp3>>32 mov_eax_memoffs32((unsigned long *)(dst->f.r.rs)+1); mul_m32((unsigned long *)(dst->f.r.rt)+1); add_reg32_reg32(EAX, ESI); adc_reg32_imm32(EDX, 0); // EDX:EAX = temp4 add_reg32_reg32(EAX, ECX); adc_reg32_imm32(EDX, 0); // EDX:EAX = result3 mov_memoffs32_eax((unsigned long *)(&hi)); mov_m32_reg32((unsigned long *)(&hi)+1, EDX); #endif }
void gendmultu(void) { #ifdef INTERPRET_DMULTU gencallinterp((unsigned int)cached_interpreter_table.DMULTU, 0); #else free_all_registers(); simplify_access(); mov_eax_memoffs32((unsigned int *)g_dev.r4300.recomp.dst->f.r.rs); mul_m32((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); // EDX:EAX = temp1 mov_memoffs32_eax((unsigned int *)(r4300_mult_lo())); mov_reg32_reg32(EBX, EDX); // EBX = temp1>>32 mov_eax_memoffs32((unsigned int *)g_dev.r4300.recomp.dst->f.r.rs); mul_m32((unsigned int *)(g_dev.r4300.recomp.dst->f.r.rt)+1); add_reg32_reg32(EBX, EAX); adc_reg32_imm32(EDX, 0); mov_reg32_reg32(ECX, EDX); // ECX:EBX = temp2 mov_eax_memoffs32((unsigned int *)(g_dev.r4300.recomp.dst->f.r.rs)+1); mul_m32((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); // EDX:EAX = temp3 add_reg32_reg32(EBX, EAX); adc_reg32_imm32(ECX, 0); // ECX:EBX = result2 mov_m32_reg32((unsigned int*)(r4300_mult_lo())+1, EBX); mov_reg32_reg32(ESI, EDX); // ESI = temp3>>32 mov_eax_memoffs32((unsigned int *)(g_dev.r4300.recomp.dst->f.r.rs)+1); mul_m32((unsigned int *)(g_dev.r4300.recomp.dst->f.r.rt)+1); add_reg32_reg32(EAX, ESI); adc_reg32_imm32(EDX, 0); // EDX:EAX = temp4 add_reg32_reg32(EAX, ECX); adc_reg32_imm32(EDX, 0); // EDX:EAX = result3 mov_memoffs32_eax((unsigned int *)(r4300_mult_hi())); mov_m32_reg32((unsigned int *)(r4300_mult_hi())+1, EDX); #endif }