// Module initialisation void AnalogInInit() { #if SAM3XA || SAM4S pmc_enable_periph_clk(ID_ADC); adc_init(ADC, SystemCoreClock, 2000000, ADC_STARTUP_TIME_12); // 2MHz clock adc_configure_timing(ADC, 3, ADC_SETTLING_TIME_3, 1); // Add transfer time adc_configure_trigger(ADC, ADC_TRIG_SW, 0); // Disable hardware trigger adc_disable_interrupt(ADC, 0xFFFFFFFF); // Disable all ADC interrupts adc_disable_all_channel(ADC); #elif SAM4E || SAME70 afec_enable(AFEC0); afec_enable(AFEC1); afec_config cfg; afec_get_config_defaults(&cfg); #if 0 // these are probably not needed, the defaults should be OK // cfg.afec_clock = 2000000UL; // reduce clock frequency // cfg.settling_time = AFEC_SETTLING_TIME_3; #endif while (afec_init(AFEC0, &cfg) != STATUS_OK) { (void)afec_get_latest_value(AFEC0); } while (afec_init(AFEC1, &cfg) != STATUS_OK) { (void)afec_get_latest_value(AFEC1); } afec_disable_interrupt(AFEC0, AFEC_INTERRUPT_ALL); afec_disable_interrupt(AFEC1, AFEC_INTERRUPT_ALL); afec_set_trigger(AFEC0, AFEC_TRIG_SW); afec_set_trigger(AFEC1, AFEC_TRIG_SW); #endif }
/** * \brief AFEC interrupt callback function. */ static void afec_data_ready(void) { g_afec_sample_data.value = afec_get_latest_value(AFEC0); g_afec_sample_data.is_done = true; }
/** * \brief AFEC0 DRDY interrupt callback function. */ static void afec0_diff_data_ready(void) { g_afec0_sample_data = afec_get_latest_value(AFEC0); puts("AFEC0 Channel Differential Voltage:"); print_float(g_afec0_sample_data * VOLT_REF / g_max_digital - 1650); }
/** * \brief AFEC1 DRDY interrupt callback function. */ static void afec1_data_ready(void) { g_afec1_sample_data = afec_get_latest_value(AFEC1); puts("AFEC1 Channel Voltage:"); print_float(g_afec1_sample_data * VOLT_REF / g_max_digital); }
static void afec1_data_ready(void) { g_afec1_sample_data = afec_get_latest_value(AFEC1); is_conversion_done = true; }