static void ag71xx_hw_init(struct ag71xx *ag) { struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); udelay(20); ar71xx_device_stop(pdata->reset_bit); mdelay(100); ar71xx_device_start(pdata->reset_bit); mdelay(100); /* setup MAC configuration registers */ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); /* setup max frame length */ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN); /* setup MII interface type */ ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); /* setup FIFO configuration registers */ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); ag71xx_dma_reset(ag); }
static void ag71xx_hw_init(struct ag71xx *ag) { struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); udelay(20); ar71xx_device_stop(pdata->reset_bit); mdelay(100); ar71xx_device_start(pdata->reset_bit); mdelay(100); ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); /* TODO: set max packet size */ ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, 0x00001f00); ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff); ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, 0x0007ffef); }