void sw_ahci_dump_reg(struct device *dev)
{
struct ata_host *host = dev_get_drvdata(dev);
struct ahci_host_priv *hpriv = host->private_data;
u32 base = (u32)hpriv->mmio;
int i = 0;
for(i=0; i<0x200; i+=0x10) {
printk("0x%3x = 0x%x, 0x%3x = 0x%x, 0x%3x = 0x%x, 0x%3x = 0x%x\n", i, ahci_readl(base, i), i+4, ahci_readl(base, i+4), i+8, ahci_readl(base, i+8), i+12, ahci_readl(base, i+12));
}
}
static int sw_ahci_start(struct device *dev, void __iomem *addr)
{
struct clk *hclk;
struct clk *mclk;
u32 pio_hdle = 0;
int ctrl = 0;
int rc = 0;
script_parser_fetch(sw_ahci_para_name, sw_ahci_used_name, &ctrl, sizeof(int));
if(!ctrl)
{
dev_err(dev, "AHCI is disable\n");
rc = -EINVAL;
goto err2;
}
/*Enable mclk and hclk for AHCI*/
mclk = clk_get(dev, sw_ahci_mclk_name);
if (IS_ERR(mclk))
{
dev_err(dev, "Error to get module clk for AHCI\n");
rc = -EINVAL;
goto err2;
}
hclk = clk_get(dev, sw_ahci_hclk_name);
if (IS_ERR(hclk))
{
dev_err(dev, "Error to get ahb clk for AHCI\n");
rc = -EINVAL;
goto err1;
}
/*Enable SATA Clock in SATA PLL*/
ahci_writel(CCMU_PLL6_VBASE, 0, ahci_readl(CCMU_PLL6_VBASE, 0)|(0x1<<14));
clk_enable(mclk);
clk_enable(hclk);
sw_ahci_phy_init((unsigned int)addr);
pio_hdle = gpio_request_ex(sw_ahci_para_name, NULL);
if(pio_hdle)
{
gpio_write_one_pin_value(pio_hdle, 1, sw_ahci_gpio_name);
gpio_release(pio_hdle, 2);
}
clk_put(hclk);
err1:
clk_put(mclk);
err2:
return rc;
}
static int sw_ahci_start(struct device *dev, void __iomem *addr)
{
struct clk *hclk;
struct clk *mclk;
int rc = 0;
/*Enable mclk and hclk for AHCI*/
mclk = clk_get(dev, sw_ahci_mclk_name);
if (IS_ERR(mclk))
{
dev_err(dev, "Error to get module clk for AHCI\n");
rc = -EINVAL;
goto err2;
}
hclk = clk_get(dev, sw_ahci_hclk_name);
if (IS_ERR(hclk))
{
dev_err(dev, "Error to get ahb clk for AHCI\n");
rc = -EINVAL;
goto err1;
}
/*Enable SATA Clock in SATA PLL*/
ahci_writel(CCMU_PLL6_VBASE, 0, ahci_readl(CCMU_PLL6_VBASE, 0)|(0x1<<14));
clk_enable(mclk);
clk_enable(hclk);
sw_ahci_phy_init((unsigned int)addr);
clk_put(hclk);
err1:
clk_put(mclk);
err2:
return rc;
}
static int sw_ahci_phy_init(unsigned int base)
{
unsigned int tmp;
const unsigned int timeout_val = 0x100000;
unsigned int timeout = timeout_val;
for(tmp=0; tmp<0x1000; tmp++);
SW_AHCI_ACCESS_LOCK(base, 0);
tmp = ahci_readl(base, SW_AHCI_PHYCS1R_OFFSET);
tmp |= (0x1<<19);
ahci_writel(base, SW_AHCI_PHYCS1R_OFFSET, tmp);
tmp = ahci_readl(base, SW_AHCI_PHYCS0R_OFFSET);
tmp |= 0x1<<23;
tmp |= 0x1<<18;
tmp &= ~(0x7<<24);
tmp |= 0x5<<24;
ahci_writel(base, SW_AHCI_PHYCS0R_OFFSET, tmp);
tmp = ahci_readl(base, SW_AHCI_PHYCS1R_OFFSET);
tmp &= ~(0x3<<16);
tmp |= (0x2<<16);
tmp &= ~(0x1f<<8);
tmp |= (6<<8);
tmp &= ~(0x3<<6);
tmp |= (2<<6);
ahci_writel(base, SW_AHCI_PHYCS1R_OFFSET, tmp);
tmp = ahci_readl(base, SW_AHCI_PHYCS1R_OFFSET);
tmp |= (0x1<<28);
tmp |= (0x1<<15);
ahci_writel(base, SW_AHCI_PHYCS1R_OFFSET, tmp);
tmp = ahci_readl(base, SW_AHCI_PHYCS1R_OFFSET);
tmp &= ~(0x1<<19);
ahci_writel(base, SW_AHCI_PHYCS1R_OFFSET, tmp);
tmp = ahci_readl(base, SW_AHCI_PHYCS0R_OFFSET);
tmp &= ~(0x7<<20);
tmp |= (0x03<<20);
ahci_writel(base, SW_AHCI_PHYCS0R_OFFSET, tmp);
tmp = ahci_readl(base, SW_AHCI_PHYCS2R_OFFSET);
tmp &= ~(0x1f<<5);
tmp |= (0x19<<5);
ahci_writel(base, SW_AHCI_PHYCS2R_OFFSET, tmp);
for(tmp=0; tmp<0x1000; tmp++);
tmp = ahci_readl(base, SW_AHCI_PHYCS0R_OFFSET);
tmp |= 0x1<<19;
ahci_writel(base, SW_AHCI_PHYCS0R_OFFSET, tmp);
timeout = timeout_val;
do{
tmp = ahci_readl(base, SW_AHCI_PHYCS0R_OFFSET);
timeout --;
if(!timeout) break;
}while((tmp&(0x7<<28))!=(0x02<<28));
if(!timeout)
{
printk("SATA AHCI Phy Power Failed!!\n");
}
tmp = ahci_readl(base, SW_AHCI_PHYCS2R_OFFSET);
tmp |= 0x1<<24;
ahci_writel(base, SW_AHCI_PHYCS2R_OFFSET, tmp);
timeout = timeout_val;
do{
tmp = ahci_readl(base, SW_AHCI_PHYCS2R_OFFSET);
timeout --;
if(!timeout) break;
}while(tmp&(0x1<<24));
if(!timeout)
{
printk("SATA AHCI Phy Calibration Failed!!\n");
}
for(tmp=0; tmp<0x3000; tmp++);
SW_AHCI_ACCESS_LOCK(base, 0x07);
return 0;
}
