*/void
mono_gc_memmove_aligned (void *dest, const void *src, size_t size)
{
g_assert (unaligned_bytes (dest) == 0);
g_assert (unaligned_bytes (src) == 0);
/*
If we're copying less than a word we don't need to worry about word tearing
so we bailout to memmove early.
*/
if (size < sizeof(void*)) {
memmove (dest, src, size);
return;
}
/*
* A bit of explanation on why we align only dest before doing word copies.
* Pointers to managed objects must always be stored in word aligned addresses, so
* even if dest is misaligned, src will be by the same amount - this ensure proper atomicity of reads.
*
* We don't need to case when source and destination have different alignments since we only do word stores
* using memmove, which must handle it.
*/
if (dest > src && ((size_t)((char*)dest - (char*)src) < size)) { /*backward copy*/
volatile char *p = (char*)dest + size;
char *s = (char*)src + size;
char *start = (char*)dest;
char *align_end = MAX((char*)dest, (char*)align_down (p));
char *word_start;
size_t bytes_to_memmove;
while (p > align_end)
*--p = *--s;
word_start = (char *)align_up (start);
bytes_to_memmove = p - word_start;
p -= bytes_to_memmove;
s -= bytes_to_memmove;
MEMMOVE_WORDS_DOWNWARD (p, s, bytes_to_words (bytes_to_memmove));
} else {
volatile char *d = (char*)dest;
const char *s = (const char*)src;
size_t tail_bytes;
/* copy all words with memmove */
MEMMOVE_WORDS_UPWARD (d, s, bytes_to_words (align_down (size)));
tail_bytes = unaligned_bytes (size);
if (tail_bytes) {
d += (size_t)align_down (size);
s += (size_t)align_down (size);
do {
*d++ = *s++;
} while (--tail_bytes);
}
}
}
static uint32_t
getAlignedBlockSize(virt_ptr<MEMExpHeapBlock> block,
uint32_t alignment,
MEMExpHeapDirection dir)
{
if (dir == MEMExpHeapDirection::FromStart) {
auto dataStart = virt_cast<uint8_t *>(block) + sizeof(MEMExpHeapBlock);
auto dataEnd = dataStart + block->blockSize;
auto alignedDataStart = align_up(dataStart, alignment);
if (alignedDataStart >= dataEnd) {
return 0;
}
return static_cast<uint32_t>(dataEnd - alignedDataStart);
} else if (dir == MEMExpHeapDirection::FromEnd) {
auto dataStart = virt_cast<uint8_t *>(block) + sizeof(MEMExpHeapBlock);
auto dataEnd = dataStart + block->blockSize;
auto alignedDataEnd = align_down(dataEnd, alignment);
if (alignedDataEnd <= dataStart) {
return 0;
}
return static_cast<uint32_t>(alignedDataEnd - dataStart);
} else {
decaf_abort("Unexpected ExpHeap direction");
}
}
/**
* mono_gc_bzero_aligned:
* @dest: address to start to clear
* @size: size of the region to clear
*
* Zero @size bytes starting at @dest.
* The address of @dest MUST be aligned to word boundaries
*
* FIXME borrow faster code from some BSD libc or bionic
*/
void
mono_gc_bzero_aligned (void *dest, size_t size)
{
volatile char *d = (char*)dest;
size_t tail_bytes, word_bytes;
g_assert (unaligned_bytes (dest) == 0);
/* copy all words with memmove */
word_bytes = (size_t)align_down (size);
switch (word_bytes) {
case sizeof (void*) * 1:
BZERO_WORDS (d, 1);
break;
case sizeof (void*) * 2:
BZERO_WORDS (d, 2);
break;
case sizeof (void*) * 3:
BZERO_WORDS (d, 3);
break;
case sizeof (void*) * 4:
BZERO_WORDS (d, 4);
break;
default:
BZERO_WORDS (d, bytes_to_words (word_bytes));
}
tail_bytes = unaligned_bytes (size);
if (tail_bytes) {
d += word_bytes;
do {
*d++ = 0;
} while (--tail_bytes);
}
}
/**
* mem_alloc_pages - allocates pages of memory
* @nr: the number of pages to allocate
* @size: the page size (4KB, 2MB, or 1GB)
* @mask: the numa node mask
* @numa_policy: the numa policy
*
* Returns a pointer (virtual address) to a page, or NULL if fail.
*/
void *mem_alloc_pages(int nr, int size, struct bitmask *mask, int numa_policy)
{
void *base;
switch (size) {
case PGSIZE_4KB:
base = NULL;
case PGSIZE_2MB:
spin_lock(&mem_lock);
mem_pos -= PGSIZE_2MB * nr;
base = (void *) mem_pos;
spin_unlock(&mem_lock);
break;
case PGSIZE_1GB:
spin_lock(&mem_lock);
mem_pos = align_down(mem_pos - PGSIZE_1GB * nr, PGSIZE_1GB);
base = (void *) mem_pos;
spin_unlock(&mem_lock);
break;
default:
return MAP_FAILED;
}
return __mem_alloc_pages(base, nr, size, mask, numa_policy);
}
//----释放准静态分配的内存块---------------------------------------------------
//功能：释放准静态分配的一个内存块，在heap的cession中查找，如果待释放的内存是从该
// session分配的最后一块内存，释放之。
//参数：pl_mem，待释放的内存块指针
// Heap，指定从这个堆中释放。
//返回：true = 成功释放，false = 释放失败
//备注: 1.准静态分配与静态内存分配类似,没有保护措施,正确性要程序员自己保证.这种
// 分配方法也不会引起阻塞,在执行module_init_heap_dynamic之前,所有的内存分配
// 均采用准静态分配
// 2.本函数在初始化完成之前调用,中断尚未开启,无需考虑关闭中断的问题.
//-----------------------------------------------------------------------------
void __M_StaticFreeHeap(void * pl_mem,struct tagHeapCB *Heap)
{
atom_low_t atom_m;
struct tagHeapCession *Cession;
ptu32_t *psize;
if(pl_mem == NULL)
return ;
if(pl_mem != (void *)align_up(Heap->AlignSize,pl_mem))//不符合对齐要求的指针
return ;
Cession = Heap->Cession;
atom_m = Int_LowAtomStart();
while(Cession != NULL)
{
psize = (ptu32_t *)pl_mem;
psize--;
if( (*psize + (u8*)pl_mem) == Cession->heap_bottom)
{
//pl_mem是从该cession最后分配的内存，可以释放
Cession->heap_bottom = (void*)align_down(Heap->AlignSize,psize);
break;
}
Cession = Cession->Next;
}
Int_LowAtomEnd(atom_m);
return ;
}
int down_arrow(int **tbl, int len)
{
int i;
int j;
int cpt;
cpt = 0;
while (cpt < len)
{
i = (len * (len - 1)) + cpt;
while (i > cpt)
{
j = i - len;
while (j >= cpt)
{
if (add_values(tbl, i, j))
break ;
j -= len;
}
i -= len;
}
cpt++;
}
align_down(tbl, len);
return (0);
}
/* Align_up restrictions apply here to */
static void align_range_up(struct cach_range *range, u32 alignment)
{
if (!is_non_empty_range(range))
return;
range->start = align_down(range->start, alignment);
range->end = align_up(range->end, alignment);
}
Result
Thread::start(ThreadEntryFn entry,
phys_ptr<void> context,
phys_ptr<uint8_t> stackTop,
uint32_t stackSize,
ThreadPriority priority)
{
auto tlsDataSize = tlsGetDataSize();
auto userStackTop = stackTop;
// Allocate TLS data from stack
stackTop = align_down(stackTop - tlsDataSize, 8);
auto tlsData = phys_cast<void *>(stackTop);
tlsInitialiseData(tlsData);
// Allocate thread start context from stack
stackTop = align_down(stackTop - sizeof(ThreadStartData), 8);
auto threadStartData = phys_cast<ThreadStartData *>(stackTop);
threadStartData->entry = entry;
threadStartData->context = context;
threadStartData->tlsData = tlsData;
// Calculate new stack size
stackSize -= static_cast<uint32_t>(userStackTop - stackTop);
auto error = IOS_CreateThread(threadEntryPoint,
threadStartData,
stackTop,
stackSize,
priority,
ThreadFlags::AllocateTLS);
if (error < ::ios::Error::OK) {
return ios::convertError(error);
}
mThreadId = static_cast<ThreadId>(error);
error = IOS_StartThread(mThreadId);
if (error < ::ios::Error::OK) {
return ios::convertError(error);
}
mJoined = false;
return ios::ResultOK;
}
static void
mark_bits_in_range (char *space_bitmap, char *start, char *end)
{
start = align_down (start, SGEN_TO_SPACE_GRANULE_BITS);
end = align_up (end, SGEN_TO_SPACE_GRANULE_BITS);
for (;start < end; start += SGEN_TO_SPACE_GRANULE_IN_BYTES)
mark_bit (space_bitmap, start);
}
static u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnptr)
{
u32 insn;
insn = le32_to_cpu(*altinsnptr);
if (aarch64_insn_is_branch_imm(insn)) {
s32 offset = aarch64_get_branch_offset(insn);
unsigned long target;
target = (unsigned long)altinsnptr + offset;
/*
* If we're branching inside the alternate sequence,
* do not rewrite the instruction, as it is already
* correct. Otherwise, generate the new instruction.
*/
if (branch_insn_requires_update(alt, target)) {
offset = target - (unsigned long)insnptr;
insn = aarch64_set_branch_offset(insn, offset);
}
} else if (aarch64_insn_is_adrp(insn)) {
s32 orig_offset, new_offset;
unsigned long target;
/*
* If we're replacing an adrp instruction, which uses PC-relative
* immediate addressing, adjust the offset to reflect the new
* PC. adrp operates on 4K aligned addresses.
*/
orig_offset = aarch64_insn_adrp_get_offset(insn);
target = align_down(altinsnptr, SZ_4K) + orig_offset;
new_offset = target - align_down(insnptr, SZ_4K);
insn = aarch64_insn_adrp_set_offset(insn, new_offset);
} else if (aarch64_insn_uses_literal(insn)) {
/*
* Disallow patching unhandled instructions using PC relative
* literal addresses
*/
BUG();
}
return insn;
}
static int
read_cb (void *buf, size_t size, size_t nelem, void *stream)
{
iobuf_t *iob = (iobuf_t *) stream;
size_t count = size * nelem;
if (count > iob->length - iob->position)
count = align_down(iob->length - iob->position, size);
memcpy(buf, iob->data, count);
iob->position += count;
return count / size;
}
static void
init_nursery (SgenFragmentAllocator *allocator, char *start, char *end)
{
int alloc_quote = (int)((end - start) * alloc_ratio);
promotion_barrier = align_down (start + alloc_quote, 3);
sgen_fragment_allocator_add (allocator, start, promotion_barrier);
sgen_fragment_allocator_add (&collector_allocator, promotion_barrier, end);
region_age_size = (end - start) >> SGEN_TO_SPACE_GRANULE_BITS;
region_age = g_malloc0 (region_age_size);
}
//------------------------------------------------------------------------
inline int pe_loader_t::process_sections(linput_t *li, off_t first_sec_pos, int nobjs, pe_section_visitor_t &psv)
{
transvec.qclear();
qvector <pesection_t> sec_headers;
// does the file layout match memory layout?
bool alt_align = pe.objalign == pe.filealign && pe.objalign < PAGE_SIZE;
for ( int i=0; i < nobjs; i++ )
{
pesection_t& sh = sec_headers.push_back();
qlseek(li, first_sec_pos + i*sizeof(pesection_t));
lread(li, &sh, sizeof(sh));
if ( sh.s_vaddr != uint32(sh.s_scnptr)
|| sh.s_vsize > sh.s_psize )
alt_align = false;
}
if ( alt_align )
// according to Ivan Teblin from AVERT Labs, such files are
// mapped by Windows as-is and not section by section
// we mimic that behaviour
psv.load_all();
int off_align = alt_align ? pe.filealign : FILEALIGN;
if ( pe.is_efi() )
off_align = 1;
for ( int i=0; i < nobjs; i++ )
{
pesection_t &sh = sec_headers[i];
uint32 scnptr = align_down(sh.s_scnptr, off_align);//pe.align_down_in_file(sh.s_scnptr);
transl_t &tr = transvec.push_back();
tr.start = sh.s_vaddr;
tr.psize = sh.get_psize(pe);
tr.end = pe.align_up_in_file(uint32(sh.s_vaddr + tr.psize));
tr.pos = scnptr;
int code = psv.visit_section(sh, scnptr);
if ( code != 0 )
return code;
}
if ( nobjs == 0 )
{
// add mapping for the header
transl_t &tr = transvec.push_back();
tr.start = 0;
tr.psize = qlsize(li);
tr.end = pe.align_up_in_file(pe.imagesize);
tr.pos = 0;
}
return 0;
}
MEMHeapHandle
MEMCreateExpHeapEx(virt_ptr<void> base,
uint32_t size,
uint32_t flags)
{
decaf_check(base);
auto heapData = virt_cast<uint8_t *>(base);
auto alignedStart = align_up(heapData, 4);
auto alignedEnd = align_down(heapData + size, 4);
if (alignedEnd < alignedStart || alignedEnd - alignedStart < 0x6C) {
// Not enough room for the header
return nullptr;
}
// Get our heap header
auto heap = virt_cast<MEMExpHeap *>(alignedStart);
// Register Heap
internal::registerHeap(virt_addrof(heap->header),
MEMHeapTag::ExpandedHeap,
alignedStart + sizeof(MEMExpHeap),
alignedEnd,
static_cast<MEMHeapFlags>(flags));
// Create an initial block of the data
auto dataStart = alignedStart + sizeof(MEMExpHeap);
auto firstBlock = virt_cast<MEMExpHeapBlock *>(dataStart);
firstBlock->attribs = MEMExpHeapBlockAttribs::get(0);
firstBlock->blockSize = static_cast<uint32_t>((alignedEnd - dataStart) - sizeof(MEMExpHeapBlock));
firstBlock->next = nullptr;
firstBlock->prev = nullptr;
firstBlock->tag = FreeTag;
heap->freeList.head = firstBlock;
heap->freeList.tail = firstBlock;
heap->usedList.head = nullptr;
heap->usedList.tail = nullptr;
heap->groupId = uint16_t { 0 };
heap->attribs = MEMExpHeapAttribs::get(0);
return virt_cast<MEMHeapHeader *>(heap);
}
void context::call(void *f, void *arg, void *stack) {
// Get the current context, which we will then modify to call the
// given function.
swap(*this);
// set up the stack
uint64_t *sp = (uint64_t *)stack;
sp = align_down(sp);
// The final return address. 0 indicates the bottom of the stack
*--sp = 0;
regs.data[RUSTRT_ARG0] = (uint64_t)arg;
regs.data[RUSTRT_RSP] = (uint64_t)sp;
regs.data[RUSTRT_IP] = (uint64_t)f;
// Last base pointer on the stack should be 0
regs.data[RUSTRT_RBP] = 0;
}
static void
prepare_to_space (char *to_space_bitmap, int space_bitmap_size)
{
SgenFragment **previous, *frag;
memset (to_space_bitmap, 0, space_bitmap_size);
memset (age_alloc_buffers, 0, sizeof (age_alloc_buffers));
previous = &collector_allocator.alloc_head;
for (frag = *previous; frag; frag = *previous) {
char *start = align_up (frag->fragment_next, SGEN_TO_SPACE_GRANULE_BITS);
char *end = align_down (frag->fragment_end, SGEN_TO_SPACE_GRANULE_BITS);
/* Fragment is too small to be usable. */
if ((end - start) < SGEN_MAX_NURSERY_WASTE) {
sgen_clear_range (frag->fragment_next, frag->fragment_end);
frag->fragment_next = frag->fragment_end = frag->fragment_start;
*previous = frag->next;
continue;
}
/*
We need to insert 3 phony objects so the fragments build step can correctly
walk the nursery.
*/
/* Clean the fragment range. */
sgen_clear_range (start, end);
/* We need a phony object in between the original fragment start and the effective one. */
if (start != frag->fragment_next)
sgen_clear_range (frag->fragment_next, start);
/* We need an phony object in between the new fragment end and the original fragment end. */
if (end != frag->fragment_end)
sgen_clear_range (end, frag->fragment_end);
frag->fragment_start = frag->fragment_next = start;
frag->fragment_end = end;
mark_bits_in_range (to_space_bitmap, start, end);
previous = &frag->next;
}
}
void context::call(void *f, void *arg, void *stack)
{
// Get the current context, which we will then modify to call the
// given function.
swap(*this);
// set up the stack
uint32_t *sp = (uint32_t *)stack;
sp = align_down(sp);
// The final return address. 0 indicates the bottom of the stack
// sp of mips o32 is 8-byte aligned
sp -= 2;
*sp = 0;
regs.data[4] = (uint32_t)arg;
regs.data[29] = (uint32_t)sp;
regs.data[25] = (uint32_t)f;
regs.data[31] = (uint32_t)f;
// Last base pointer on the stack should be 0
}
static virt_ptr<MEMExpHeapBlock>
createUsedBlockFromFreeBlock(virt_ptr<MEMExpHeap> heap,
virt_ptr<MEMExpHeapBlock> freeBlock,
uint32_t size,
uint32_t alignment,
MEMExpHeapDirection dir)
{
auto expHeapAttribs = heap->attribs.value();
auto freeBlockAttribs = freeBlock->attribs.value();
auto freeBlockPrev = freeBlock->prev;
auto freeMemStart = getBlockMemStart(freeBlock);
auto freeMemEnd = getBlockMemEnd(freeBlock);
// Free blocks should never have alignment...
decaf_check(!freeBlockAttribs.alignment());
removeBlock(virt_addrof(heap->freeList), freeBlock);
// Find where we are going to start
auto alignedDataStart = virt_ptr<uint8_t> { };
if (dir == MEMExpHeapDirection::FromStart) {
alignedDataStart = align_up(freeMemStart + sizeof(MEMExpHeapBlock), alignment);
} else if (dir == MEMExpHeapDirection::FromEnd) {
alignedDataStart = align_down(freeMemEnd - size, alignment);
} else {
decaf_abort("Unexpected ExpHeap direction");
}
// Grab the block header pointer and validate everything is sane
auto alignedBlock = virt_cast<MEMExpHeapBlock *>(alignedDataStart) - 1;
decaf_check(alignedDataStart - sizeof(MEMExpHeapBlock) >= freeMemStart);
decaf_check(alignedDataStart + size <= freeMemEnd);
// Calculate the alignment waste
auto topSpaceRemain = (alignedDataStart - freeMemStart) - sizeof(MEMExpHeapBlock);
auto bottomSpaceRemain = static_cast<uint32_t>((freeMemEnd - alignedDataStart) - size);
if (expHeapAttribs.reuseAlignSpace() || dir == MEMExpHeapDirection::FromEnd) {
// If the user wants to reuse the alignment space, or we allocated from the bottom,
// we should try to release the top space back to the heap free list.
if (topSpaceRemain > sizeof(MEMExpHeapBlock) + 4) {
// We have enough room to put some of the memory back to the free list
freeBlock = virt_cast<MEMExpHeapBlock *>(freeMemStart);
freeBlock->attribs = MEMExpHeapBlockAttribs::get(0);
freeBlock->blockSize = static_cast<uint32_t>(topSpaceRemain - sizeof(MEMExpHeapBlock));
freeBlock->next = nullptr;
freeBlock->prev = nullptr;
freeBlock->tag = FreeTag;
insertBlock(virt_addrof(heap->freeList), freeBlockPrev, freeBlock);
topSpaceRemain = 0;
}
}
if (expHeapAttribs.reuseAlignSpace() || dir == MEMExpHeapDirection::FromStart) {
// If the user wants to reuse the alignment space, or we allocated from the top,
// we should try to release the bottom space back to the heap free list.
if (bottomSpaceRemain > sizeof(MEMExpHeapBlock) + 4) {
// We have enough room to put some of the memory back to the free list
freeBlock = virt_cast<MEMExpHeapBlock *>(freeMemEnd - bottomSpaceRemain);
freeBlock->attribs = MEMExpHeapBlockAttribs::get(0);
freeBlock->blockSize = static_cast<uint32_t>(bottomSpaceRemain - sizeof(MEMExpHeapBlock));
freeBlock->next = nullptr;
freeBlock->prev = nullptr;
freeBlock->tag = FreeTag;
insertBlock(virt_addrof(heap->freeList), freeBlockPrev, freeBlock);
bottomSpaceRemain = 0;
}
}
// Update the structure with the new allocation
alignedBlock->attribs = MEMExpHeapBlockAttribs::get(0)
.alignment(static_cast<uint32_t>(topSpaceRemain))
.allocDir(dir);
alignedBlock->blockSize = size + bottomSpaceRemain;
alignedBlock->prev = nullptr;
alignedBlock->next = nullptr;
alignedBlock->tag = UsedTag;
insertBlock(virt_addrof(heap->usedList), nullptr, alignedBlock);
if (heap->header.flags & MEMHeapFlags::ZeroAllocated) {
memset(alignedDataStart, 0, size);
} else if (heap->header.flags & MEMHeapFlags::DebugMode) {
auto fillVal = MEMGetFillValForHeap(MEMHeapFillType::Allocated);
memset(alignedDataStart, fillVal, size);
}
return alignedBlock;
}
void swizzle_32bpp(uint32_t *dest, uint32_t dx, uint32_t dy, uint32_t dw, uint32_t dh,
const uint32_t *src, uint32_t sw, uint32_t sh, uint32_t spitch)
{
// Innermost loop processes 4x4 pixel tiles at a time.
static const uint32_t inner_tile_w = 4;
static const uint32_t inner_tile_h = 4;
// At 32 bits/pixel, this works out to 64 bytes - a full cache line.
// Depending on the final implementation, you might want to process slightly larger
// blocks (e.g. 8x4 or 8x8) at a time to amortize overhead better.
//
// The innermost loop here knows about the tile layout; the rest of the code is
// fully generic and only uses the swizzle_* functions to determine the layout!
uint32_t dx0 = dx;
uint32_t dx1 = align_up(dx, inner_tile_w);
uint32_t dx2 = align_down(dx + sw, inner_tile_w);
uint32_t dx3 = dx + sw;
uint32_t dy0 = dy;
uint32_t dy1 = align_up(dy, inner_tile_h);
uint32_t dy2 = align_down(dy + sh, inner_tile_h);
uint32_t dy3 = dy + sh;
// if we don't cover any full tiles, use the small loop
if (dx2 <= dx1 || dy2 <= dy1) {
swizzle_32bpp_small(dest, dx, dy, dw, dh, src, sw, sh, spitch);
return;
}
// vertical slice [dy0,dy1)
if (dy0 < dy1) {
swizzle_32bpp_small(dest, dx0, dy0, dw, dh, src, sw, dy1 - dy0, spitch);
src += (dy1 - dy0) * spitch;
}
// vertical slice [dy1,dy2) - tile aligned in y
if (dx0 < dx1) // leftovers at left side?
swizzle_32bpp_small(dest, dx0, dy1, dw, dh, src, dx1 - dx0, dy2 - dy1, spitch);
// center part (fully tile aligned in dest)
{
ptrdiff_t x_step4_bytes = swizzle_x_tile(~0u * inner_tile_w) * sizeof(uint32_t);
uintptr_t y_step4 = swizzle_y(~0u * inner_tile_h);
uintptr_t incr_y = swizzle_x_tile(align_up(dw, swizzle_outermost_tile_w()));
uintptr_t offs_x0_tile = swizzle_x_tile(dx1) + incr_y * (dy1 / swizzle_outermost_tile_h());
uintptr_t offs_y = swizzle_y(dy1);
const uint32_t *src_line = src + (dx1 - dx0);
for (uint32_t y = dy1; y < dy2; y += inner_tile_h) {
char *dest_line = (char *) (dest + offs_y);
uintptr_t offs_x = offs_x0_tile * sizeof(uint32_t); // convert to bytes
for (uint32_t x = dx1; x < dx2; x += inner_tile_w) {
// NB for this loop you really want to make sure the generated code is
// good (or possibly hand-write assembly code); this is just for illustration.
pixel4_t row0 = loadpixel4u(src_line);
pixel4_t row1 = loadpixel4u(src_line + spitch);
pixel4_t row2 = loadpixel4u(src_line + 2*spitch);
pixel4_t row3 = loadpixel4u(src_line + 3*spitch);
uint32_t *dest_tile = (uint32_t *) (dest_line + offs_x);
storepixel4(dest_tile + 0, row0);
storepixel4(dest_tile + 4, row1);
storepixel4(dest_tile + 8, row2);
storepixel4(dest_tile + 12, row3);
offs_x = (offs_x - x_step4_bytes) & x_step4_bytes;
src_line += inner_tile_w;
}
// advance pointers
src_line += inner_tile_h * spitch - (dx2 - dx1);
offs_y = (offs_y - y_step4) & y_step4;
if (!offs_y) // wrapped into next tile row
offs_x0_tile += incr_y;
}
}
if (dx2 < dx3) // leftovers at right side?
swizzle_32bpp_small(dest, dx2, dy1, dw, dh, src + (dx2 - dx0), dx3 - dx2, dy2 - dy1, spitch);
src += (dy2 - dy1) * spitch;
// vertical slice [dy2,dy3)
if (dy2 < dy3)
swizzle_32bpp_small(dest, dx0, dy2, dw, dh, src, sw, dy3 - dy2, spitch);
}
CORE_ADDR
ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST saved_sp;
int argspace = 0; /* 0 is an initial wrong guess. */
int write_pass;
gdb_assert (tdep->wordsize == 4);
regcache_cooked_read_unsigned (regcache, gdbarch_sp_regnum (gdbarch),
&saved_sp);
/* Go through the argument list twice.
Pass 1: Figure out how much new stack space is required for
arguments and pushed values. Unlike the PowerOpen ABI, the SysV
ABI doesn't reserve any extra space for parameters which are put
in registers, but does always push structures and then pass their
address.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-float, non-vector
arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* Arguments start above the "LR save word" and "Back chain". */
int argoffset = 2 * tdep->wordsize;
/* Structures start after the arguments. */
int structoffset = argoffset + argspace;
/* If the function is returning a `struct', then the first word
(which will be passed in r3) is used for struct return
address. In that case we should advance one word and start
from r4 register to copy parameters. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (value_type (arg));
int len = TYPE_LENGTH (type);
const bfd_byte *val = value_contents (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT && len <= 8
&& !tdep->soft_float)
{
/* Floating point value converted to "double" then
passed in an FP register, when the registers run out,
8 byte aligned stack is used. */
if (freg <= 8)
{
if (write_pass)
{
/* Always store the floating point value using
the register's floating-point format. */
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum + freg);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
freg++;
}
else
{
/* The SysV ABI tells us to convert floats to
doubles before writing them to an 8 byte aligned
stack location. Unfortunately GCC does not do
that, and stores floats into 4 byte aligned
locations without converting them to doubles.
Since there is no know compiler that actually
follows the ABI here, we implement the GCC
convention. */
/* Align to 4 bytes or 8 bytes depending on the type of
the argument (float or double). */
argoffset = align_up (argoffset, len);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += len;
}
}
else if (TYPE_CODE (type) == TYPE_CODE_FLT
&& len == 16
&& !tdep->soft_float
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
{
/* IBM long double passed in two FP registers if
available, otherwise 8-byte aligned stack. */
if (freg <= 7)
{
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
val);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1,
val + 8);
}
freg += 2;
}
else
{
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += 16;
}
}
else if (len == 8
&& (TYPE_CODE (type) == TYPE_CODE_INT /* long long */
|| TYPE_CODE (type) == TYPE_CODE_FLT /* double */
|| (TYPE_CODE (type) == TYPE_CODE_DECFLOAT
&& tdep->soft_float)))
{
/* "long long" or soft-float "double" or "_Decimal64"
passed in an odd/even register pair with the low
addressed word in the odd register and the high
addressed word in the even register, or when the
registers run out an 8 byte aligned stack
location. */
if (greg > 9)
{
/* Just in case GREG was 10. */
greg = 11;
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += 8;
}
else
{
/* Must start on an odd register - r3/r4 etc. */
if ((greg & 1) == 0)
greg++;
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 0,
val + 0);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 4);
}
greg += 2;
}
}
else if (len == 16
&& ((TYPE_CODE (type) == TYPE_CODE_FLT
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
|| (TYPE_CODE (type) == TYPE_CODE_DECFLOAT
&& tdep->soft_float)))
{
/* Soft-float IBM long double or _Decimal128 passed in
four consecutive registers, or on the stack. The
registers are not necessarily odd/even pairs. */
if (greg > 7)
{
greg = 11;
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += 16;
}
else
{
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 0,
val + 0);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 4);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 2,
val + 8);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 3,
val + 12);
}
greg += 4;
}
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT && len <= 8
&& !tdep->soft_float)
{
/* 32-bit and 64-bit decimal floats go in f1 .. f8. They can
end up in memory. */
if (freg <= 8)
{
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
const gdb_byte *p;
/* 32-bit decimal floats are right aligned in the
doubleword. */
if (TYPE_LENGTH (type) == 4)
{
memcpy (regval + 4, val, 4);
p = regval;
}
else
p = val;
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, p);
}
freg++;
}
else
{
argoffset = align_up (argoffset, len);
if (write_pass)
/* Write value in the stack's parameter save area. */
write_memory (sp + argoffset, val, len);
argoffset += len;
}
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT && len == 16
&& !tdep->soft_float)
{
/* 128-bit decimal floats go in f2 .. f7, always in even/odd
pairs. They can end up in memory, using two doublewords. */
if (freg <= 6)
{
/* Make sure freg is even. */
freg += freg & 1;
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, val);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1, val + 8);
}
}
else
{
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, 16);
argoffset += 16;
}
/* If a 128-bit decimal float goes to the stack because only f7
and f8 are free (thus there's no even/odd register pair
available), these registers should be marked as occupied.
Hence we increase freg even when writing to memory. */
freg += 2;
}
else if (len == 16
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type)
&& tdep->vector_abi == POWERPC_VEC_ALTIVEC)
{
/* Vector parameter passed in an Altivec register, or
when that runs out, 16 byte aligned stack location. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
argoffset = align_up (argoffset, 16);
if (write_pass)
write_memory (sp + argoffset, val, 16);
argoffset += 16;
}
}
else if (len == 8
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type)
&& tdep->vector_abi == POWERPC_VEC_SPE)
{
/* Vector parameter passed in an e500 register, or when
that runs out, 8 byte aligned stack location. Note
that since e500 vector and general purpose registers
both map onto the same underlying register set, a
"greg" and not a "vreg" is consumed here. A cooked
write stores the value in the correct locations
within the raw register cache. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_ev0_regnum + greg, val);
greg++;
}
else
{
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, 8);
argoffset += 8;
}
}
else
{
/* Reduce the parameter down to something that fits in a
"word". */
gdb_byte word[MAX_REGISTER_SIZE];
memset (word, 0, MAX_REGISTER_SIZE);
if (len > tdep->wordsize
|| TYPE_CODE (type) == TYPE_CODE_STRUCT
|| TYPE_CODE (type) == TYPE_CODE_UNION)
{
/* Structs and large values are put in an
aligned stack slot ... */
if (TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type)
&& len >= 16)
structoffset = align_up (structoffset, 16);
else
structoffset = align_up (structoffset, 8);
if (write_pass)
write_memory (sp + structoffset, val, len);
/* ... and then a "word" pointing to that address is
passed as the parameter. */
store_unsigned_integer (word, tdep->wordsize, byte_order,
sp + structoffset);
structoffset += len;
}
else if (TYPE_CODE (type) == TYPE_CODE_INT)
/* Sign or zero extend the "int" into a "word". */
store_unsigned_integer (word, tdep->wordsize, byte_order,
unpack_long (type, val));
else
/* Always goes in the low address. */
memcpy (word, val, len);
/* Store that "word" in a register, or on the stack.
The words have "4" byte alignment. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg, word);
greg++;
}
else
{
argoffset = align_up (argoffset, tdep->wordsize);
if (write_pass)
write_memory (sp + argoffset, word, tdep->wordsize);
argoffset += tdep->wordsize;
}
}
}
/* Compute the actual stack space requirements. */
if (!write_pass)
{
/* Remember the amount of space needed by the arguments. */
argspace = argoffset;
/* Allocate space for both the arguments and the structures. */
sp -= (argoffset + structoffset);
/* Ensure that the stack is still 16 byte aligned. */
sp = align_down (sp, 16);
}
/* The psABI says that "A caller of a function that takes a
variable argument list shall set condition register bit 6 to
1 if it passes one or more arguments in the floating-point
registers. It is strongly recommended that the caller set the
bit to 0 otherwise..." Doing this for normal functions too
shouldn't hurt. */
if (write_pass)
{
ULONGEST cr;
regcache_cooked_read_unsigned (regcache, tdep->ppc_cr_regnum, &cr);
if (freg > 1)
cr |= 0x02000000;
else
cr &= ~0x02000000;
regcache_cooked_write_unsigned (regcache, tdep->ppc_cr_regnum, cr);
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, byte_order, saved_sp);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
return sp;
}
CORE_ADDR
ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
CORE_ADDR func_addr = find_function_addr (function, NULL);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST back_chain;
/* See for-loop comment below. */
int write_pass;
/* Size of the Altivec's vector parameter region, the final value is
computed in the for-loop below. */
LONGEST vparam_size = 0;
/* Size of the general parameter region, the final value is computed
in the for-loop below. */
LONGEST gparam_size = 0;
/* Kevin writes ... I don't mind seeing tdep->wordsize used in the
calls to align_up(), align_down(), etc. because this makes it
easier to reuse this code (in a copy/paste sense) in the future,
but it is a 64-bit ABI and asserting that the wordsize is 8 bytes
at some point makes it easier to verify that this function is
correct without having to do a non-local analysis to figure out
the possible values of tdep->wordsize. */
gdb_assert (tdep->wordsize == 8);
/* This function exists to support a calling convention that
requires floating-point registers. It shouldn't be used on
processors that lack them. */
gdb_assert (ppc_floating_point_unit_p (gdbarch));
/* By this stage in the proceedings, SP has been decremented by "red
zone size" + "struct return size". Fetch the stack-pointer from
before this and use that as the BACK_CHAIN. */
regcache_cooked_read_unsigned (regcache, gdbarch_sp_regnum (gdbarch),
&back_chain);
/* Go through the argument list twice.
Pass 1: Compute the function call's stack space and register
requirements.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-vector (but possibly
float) arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* The address, at which the next general purpose parameter
(integer, struct, float, ...) should be saved. */
CORE_ADDR gparam;
/* Address, at which the next Altivec vector parameter should be
saved. */
CORE_ADDR vparam;
if (!write_pass)
{
/* During the first pass, GPARAM and VPARAM are more like
offsets (start address zero) than addresses. That way
they accumulate the total stack space each region
requires. */
gparam = 0;
vparam = 0;
}
else
{
/* Decrement the stack pointer making space for the Altivec
and general on-stack parameters. Set vparam and gparam
to their corresponding regions. */
vparam = align_down (sp - vparam_size, 16);
gparam = align_down (vparam - gparam_size, 16);
/* Add in space for the TOC, link editor double word,
compiler double word, LR save area, CR save area. */
sp = align_down (gparam - 48, 16);
}
/* If the function is returning a `struct', then there is an
extra hidden parameter (which will be passed in r3)
containing the address of that struct.. In that case we
should advance one word and start from r4 register to copy
parameters. This also consumes one on-stack parameter slot. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
gparam = align_up (gparam + tdep->wordsize, tdep->wordsize);
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (value_type (arg));
const bfd_byte *val = value_contents (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) <= 8)
{
/* Floats and Doubles go in f1 .. f13. They also
consume a left aligned GREG,, and can end up in
memory. */
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
const gdb_byte *p;
/* Version 1.7 of the 64-bit PowerPC ELF ABI says:
"Single precision floating point values are mapped to
the first word in a single doubleword."
And version 1.9 says:
"Single precision floating point values are mapped to
the second word in a single doubleword."
GDB then writes single precision floating point values
at both words in a doubleword, to support both ABIs. */
if (TYPE_LENGTH (type) == 4)
{
memcpy (regval, val, 4);
memcpy (regval + 4, val, 4);
p = regval;
}
else
p = val;
/* Write value in the stack's parameter save area. */
write_memory (gparam, p, 8);
if (freg <= 13)
{
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
if (greg <= 10)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg,
regval);
}
freg++;
greg++;
/* Always consume parameter stack space. */
gparam = align_up (gparam + 8, tdep->wordsize);
}
else if (TYPE_CODE (type) == TYPE_CODE_FLT
&& TYPE_LENGTH (type) == 16
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
{
/* IBM long double stored in two doublewords of the
parameter save area and corresponding registers. */
if (write_pass)
{
if (!tdep->soft_float && freg <= 13)
{
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
val);
if (freg <= 12)
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1,
val + 8);
}
if (greg <= 10)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg,
val);
if (greg <= 9)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 8);
}
write_memory (gparam, val, TYPE_LENGTH (type));
}
freg += 2;
greg += 2;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type) <= 8)
{
/* 32-bit and 64-bit decimal floats go in f1 .. f13. They can
end up in memory. */
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
const gdb_byte *p;
/* 32-bit decimal floats are right aligned in the
doubleword. */
if (TYPE_LENGTH (type) == 4)
{
memcpy (regval + 4, val, 4);
p = regval;
}
else
p = val;
/* Write value in the stack's parameter save area. */
write_memory (gparam, p, 8);
if (freg <= 13)
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, p);
}
freg++;
greg++;
/* Always consume parameter stack space. */
gparam = align_up (gparam + 8, tdep->wordsize);
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT &&
TYPE_LENGTH (type) == 16)
{
/* 128-bit decimal floats go in f2 .. f12, always in even/odd
pairs. They can end up in memory, using two doublewords. */
if (write_pass)
{
if (freg <= 12)
{
/* Make sure freg is even. */
freg += freg & 1;
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, val);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1, val + 8);
}
write_memory (gparam, val, TYPE_LENGTH (type));
}
freg += 2;
greg += 2;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else if (TYPE_LENGTH (type) == 16 && TYPE_VECTOR (type)
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& tdep->ppc_vr0_regnum >= 0)
{
/* In the Altivec ABI, vectors go in the vector
registers v2 .. v13, or when that runs out, a vector
annex which goes above all the normal parameters.
NOTE: cagney/2003-09-21: This is a guess based on the
PowerOpen Altivec ABI. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
if (write_pass)
write_memory (vparam, val, TYPE_LENGTH (type));
vparam = align_up (vparam + TYPE_LENGTH (type), 16);
}
}
else if ((TYPE_CODE (type) == TYPE_CODE_INT
|| TYPE_CODE (type) == TYPE_CODE_ENUM
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_PTR
|| TYPE_CODE (type) == TYPE_CODE_REF)
&& TYPE_LENGTH (type) <= 8)
{
/* Scalars and Pointers get sign[un]extended and go in
gpr3 .. gpr10. They can also end up in memory. */
if (write_pass)
{
/* Sign extend the value, then store it unsigned. */
ULONGEST word = unpack_long (type, val);
/* Convert any function code addresses into
descriptors. */
if (TYPE_CODE (type) == TYPE_CODE_PTR
|| TYPE_CODE (type) == TYPE_CODE_REF)
{
struct type *target_type;
target_type = check_typedef (TYPE_TARGET_TYPE (type));
if (TYPE_CODE (target_type) == TYPE_CODE_FUNC
|| TYPE_CODE (target_type) == TYPE_CODE_METHOD)
{
CORE_ADDR desc = word;
convert_code_addr_to_desc_addr (word, &desc);
word = desc;
}
}
if (greg <= 10)
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum +
greg, word);
write_memory_unsigned_integer (gparam, tdep->wordsize,
byte_order, word);
}
greg++;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else
{
int byte;
for (byte = 0; byte < TYPE_LENGTH (type);
byte += tdep->wordsize)
{
if (write_pass && greg <= 10)
{
gdb_byte regval[MAX_REGISTER_SIZE];
int len = TYPE_LENGTH (type) - byte;
if (len > tdep->wordsize)
len = tdep->wordsize;
memset (regval, 0, sizeof regval);
/* The ABI (version 1.9) specifies that values
smaller than one doubleword are right-aligned
and those larger are left-aligned. GCC
versions before 3.4 implemented this
incorrectly; see
<http://gcc.gnu.org/gcc-3.4/powerpc-abi.html>. */
if (byte == 0)
memcpy (regval + tdep->wordsize - len,
val + byte, len);
else
memcpy (regval, val + byte, len);
regcache_cooked_write (regcache, greg, regval);
}
greg++;
}
if (write_pass)
{
/* WARNING: cagney/2003-09-21: Strictly speaking, this
isn't necessary, unfortunately, GCC appears to get
"struct convention" parameter passing wrong putting
odd sized structures in memory instead of in a
register. Work around this by always writing the
value to memory. Fortunately, doing this
simplifies the code. */
int len = TYPE_LENGTH (type);
if (len < tdep->wordsize)
write_memory (gparam + tdep->wordsize - len, val, len);
else
write_memory (gparam, val, len);
}
if (freg <= 13
&& TYPE_CODE (type) == TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type) == 1
&& TYPE_LENGTH (type) <= 16)
{
/* The ABI (version 1.9) specifies that structs
containing a single floating-point value, at any
level of nesting of single-member structs, are
passed in floating-point registers. */
while (TYPE_CODE (type) == TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type) == 1)
type = check_typedef (TYPE_FIELD_TYPE (type, 0));
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
if (TYPE_LENGTH (type) <= 8)
{
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch,
tdep->ppc_fp0_regnum);
convert_typed_floating (val, type, regval,
regtype);
regcache_cooked_write (regcache,
(tdep->ppc_fp0_regnum
+ freg),
regval);
}
freg++;
}
else if (TYPE_LENGTH (type) == 16
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
{
if (write_pass)
{
regcache_cooked_write (regcache,
(tdep->ppc_fp0_regnum
+ freg),
val);
if (freg <= 12)
regcache_cooked_write (regcache,
(tdep->ppc_fp0_regnum
+ freg + 1),
val + 8);
}
freg += 2;
}
}
}
/* Always consume parameter stack space. */
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
}
if (!write_pass)
{
/* Save the true region sizes ready for the second pass. */
vparam_size = vparam;
/* Make certain that the general parameter save area is at
least the minimum 8 registers (or doublewords) in size. */
if (greg < 8)
gparam_size = 8 * tdep->wordsize;
else
gparam_size = gparam;
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, byte_order, back_chain);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
/* Use the func_addr to find the descriptor, and use that to find
the TOC. If we're calling via a function pointer, the pointer
itself identifies the descriptor. */
{
struct type *ftype = check_typedef (value_type (function));
CORE_ADDR desc_addr = value_as_address (function);
if (TYPE_CODE (ftype) == TYPE_CODE_PTR
|| convert_code_addr_to_desc_addr (func_addr, &desc_addr))
{
/* The TOC is the second double word in the descriptor. */
CORE_ADDR toc =
read_memory_unsigned_integer (desc_addr + tdep->wordsize,
tdep->wordsize, byte_order);
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum + 2, toc);
}
}
return sp;
}
static CORE_ADDR
rs6000_lynx178_push_dummy_call (struct gdbarch *gdbarch,
struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int ii;
int len = 0;
int argno; /* current argument number */
int argbytes; /* current argument byte */
gdb_byte tmp_buffer[50];
int f_argno = 0; /* current floating point argno */
int wordsize = gdbarch_tdep (gdbarch)->wordsize;
CORE_ADDR func_addr = find_function_addr (function, NULL);
struct value *arg = 0;
struct type *type;
ULONGEST saved_sp;
/* The calling convention this function implements assumes the
processor has floating-point registers. We shouldn't be using it
on PPC variants that lack them. */
gdb_assert (ppc_floating_point_unit_p (gdbarch));
/* The first eight words of ther arguments are passed in registers.
Copy them appropriately. */
ii = 0;
/* If the function is returning a `struct', then the first word
(which will be passed in r3) is used for struct return address.
In that case we should advance one word and start from r4
register to copy parameters. */
if (struct_return)
{
regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
struct_addr);
ii++;
}
/* Effectively indirect call... gcc does...
return_val example( float, int);
eabi:
float in fp0, int in r3
offset of stack on overflow 8/16
for varargs, must go by type.
power open:
float in r3&r4, int in r5
offset of stack on overflow different
both:
return in r3 or f0. If no float, must study how gcc emulates floats;
pay attention to arg promotion.
User may have to cast\args to handle promotion correctly
since gdb won't know if prototype supplied or not. */
for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
{
int reg_size = register_size (gdbarch, ii + 3);
arg = args[argno];
type = check_typedef (value_type (arg));
len = TYPE_LENGTH (type);
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
/* Floating point arguments are passed in fpr's, as well as gpr's.
There are 13 fpr's reserved for passing parameters. At this point
there is no way we would run out of them.
Always store the floating point value using the register's
floating-point format. */
const int fp_regnum = tdep->ppc_fp0_regnum + 1 + f_argno;
gdb_byte reg_val[MAX_REGISTER_SIZE];
struct type *reg_type = register_type (gdbarch, fp_regnum);
gdb_assert (len <= 8);
convert_typed_floating (value_contents (arg), type,
reg_val, reg_type);
regcache_cooked_write (regcache, fp_regnum, reg_val);
++f_argno;
}
if (len > reg_size)
{
/* Argument takes more than one register. */
while (argbytes < len)
{
gdb_byte word[MAX_REGISTER_SIZE];
memset (word, 0, reg_size);
memcpy (word,
((char *) value_contents (arg)) + argbytes,
(len - argbytes) > reg_size
? reg_size : len - argbytes);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + 3 + ii,
word);
++ii, argbytes += reg_size;
if (ii >= 8)
goto ran_out_of_registers_for_arguments;
}
argbytes = 0;
--ii;
}
else
{
/* Argument can fit in one register. No problem. */
int adj = gdbarch_byte_order (gdbarch)
== BFD_ENDIAN_BIG ? reg_size - len : 0;
gdb_byte word[MAX_REGISTER_SIZE];
memset (word, 0, reg_size);
memcpy (word, value_contents (arg), len);
regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
}
++argno;
}
ran_out_of_registers_for_arguments:
regcache_cooked_read_unsigned (regcache,
gdbarch_sp_regnum (gdbarch),
&saved_sp);
/* Location for 8 parameters are always reserved. */
sp -= wordsize * 8;
/* Another six words for back chain, TOC register, link register, etc. */
sp -= wordsize * 6;
/* Stack pointer must be quadword aligned. */
sp = align_down (sp, 16);
/* If there are more arguments, allocate space for them in
the stack, then push them starting from the ninth one. */
if ((argno < nargs) || argbytes)
{
int space = 0, jj;
if (argbytes)
{
space += align_up (len - argbytes, 4);
jj = argno + 1;
}
else
jj = argno;
for (; jj < nargs; ++jj)
{
struct value *val = args[jj];
space += align_up (TYPE_LENGTH (value_type (val)), 4);
}
/* Add location required for the rest of the parameters. */
space = align_up (space, 16);
sp -= space;
/* This is another instance we need to be concerned about
securing our stack space. If we write anything underneath %sp
(r1), we might conflict with the kernel who thinks he is free
to use this area. So, update %sp first before doing anything
else. */
regcache_raw_write_signed (regcache,
gdbarch_sp_regnum (gdbarch), sp);
/* If the last argument copied into the registers didn't fit there
completely, push the rest of it into stack. */
if (argbytes)
{
write_memory (sp + 24 + (ii * 4),
value_contents (arg) + argbytes,
len - argbytes);
++argno;
ii += align_up (len - argbytes, 4) / 4;
}
/* Push the rest of the arguments into stack. */
for (; argno < nargs; ++argno)
{
arg = args[argno];
type = check_typedef (value_type (arg));
len = TYPE_LENGTH (type);
/* Float types should be passed in fpr's, as well as in the
stack. */
if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
{
gdb_assert (len <= 8);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + 1 + f_argno,
value_contents (arg));
++f_argno;
}
write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
ii += align_up (len, 4) / 4;
}
}
/* Set the stack pointer. According to the ABI, the SP is meant to
be set _before_ the corresponding stack space is used. On AIX,
this even applies when the target has been completely stopped!
Not doing this can lead to conflicts with the kernel which thinks
that it still has control over this not-yet-allocated stack
region. */
regcache_raw_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
/* Set back chain properly. */
store_unsigned_integer (tmp_buffer, wordsize, byte_order, saved_sp);
write_memory (sp, tmp_buffer, wordsize);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
target_store_registers (regcache, -1);
return sp;
}
CORE_ADDR
ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
CORE_ADDR func_addr = find_function_addr (function, NULL);
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
/* By this stage in the proceedings, SP has been decremented by "red
zone size" + "struct return size". Fetch the stack-pointer from
before this and use that as the BACK_CHAIN. */
const CORE_ADDR back_chain = read_sp ();
/* See for-loop comment below. */
int write_pass;
/* Size of the Altivec's vector parameter region, the final value is
computed in the for-loop below. */
LONGEST vparam_size = 0;
/* Size of the general parameter region, the final value is computed
in the for-loop below. */
LONGEST gparam_size = 0;
/* Kevin writes ... I don't mind seeing tdep->wordsize used in the
calls to align_up(), align_down(), etc. because this makes it
easier to reuse this code (in a copy/paste sense) in the future,
but it is a 64-bit ABI and asserting that the wordsize is 8 bytes
at some point makes it easier to verify that this function is
correct without having to do a non-local analysis to figure out
the possible values of tdep->wordsize. */
gdb_assert (tdep->wordsize == 8);
/* Go through the argument list twice.
Pass 1: Compute the function call's stack space and register
requirements.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-vector (but possibly
float) arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* The address, at which the next general purpose parameter
(integer, struct, float, ...) should be saved. */
CORE_ADDR gparam;
/* Address, at which the next Altivec vector parameter should be
saved. */
CORE_ADDR vparam;
if (!write_pass)
{
/* During the first pass, GPARAM and VPARAM are more like
offsets (start address zero) than addresses. That way
the accumulate the total stack space each region
requires. */
gparam = 0;
vparam = 0;
}
else
{
/* Decrement the stack pointer making space for the Altivec
and general on-stack parameters. Set vparam and gparam
to their corresponding regions. */
vparam = align_down (sp - vparam_size, 16);
gparam = align_down (vparam - gparam_size, 16);
/* Add in space for the TOC, link editor double word,
compiler double word, LR save area, CR save area. */
sp = align_down (gparam - 48, 16);
}
/* If the function is returning a `struct', then there is an
extra hidden parameter (which will be passed in r3)
containing the address of that struct.. In that case we
should advance one word and start from r4 register to copy
parameters. This also consumes one on-stack parameter slot. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
gparam = align_up (gparam + tdep->wordsize, tdep->wordsize);
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (value_type (arg));
const bfd_byte *val = value_contents (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) <= 8)
{
/* Floats and Doubles go in f1 .. f13. They also
consume a left aligned GREG,, and can end up in
memory. */
if (write_pass)
{
if (ppc_floating_point_unit_p (current_gdbarch)
&& freg <= 13)
{
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
if (greg <= 10)
{
/* The ABI states "Single precision floating
point values are mapped to the first word in
a single doubleword" and "... floating point
values mapped to the first eight doublewords
of the parameter save area are also passed in
general registers").
This code interprets that to mean: store it,
left aligned, in the general register. */
gdb_byte regval[MAX_REGISTER_SIZE];
memset (regval, 0, sizeof regval);
memcpy (regval, val, TYPE_LENGTH (type));
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg,
regval);
}
write_memory (gparam, val, TYPE_LENGTH (type));
}
/* Always consume parameter stack space. */
freg++;
greg++;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else if (TYPE_LENGTH (type) == 16 && TYPE_VECTOR (type)
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& tdep->ppc_vr0_regnum >= 0)
{
/* In the Altivec ABI, vectors go in the vector
registers v2 .. v13, or when that runs out, a vector
annex which goes above all the normal parameters.
NOTE: cagney/2003-09-21: This is a guess based on the
PowerOpen Altivec ABI. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
if (write_pass)
write_memory (vparam, val, TYPE_LENGTH (type));
vparam = align_up (vparam + TYPE_LENGTH (type), 16);
}
}
else if ((TYPE_CODE (type) == TYPE_CODE_INT
|| TYPE_CODE (type) == TYPE_CODE_ENUM
|| TYPE_CODE (type) == TYPE_CODE_PTR)
&& TYPE_LENGTH (type) <= 8)
{
/* Scalars and Pointers get sign[un]extended and go in
gpr3 .. gpr10. They can also end up in memory. */
if (write_pass)
{
/* Sign extend the value, then store it unsigned. */
ULONGEST word = unpack_long (type, val);
/* Convert any function code addresses into
descriptors. */
if (TYPE_CODE (type) == TYPE_CODE_PTR
&& TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
{
CORE_ADDR desc = word;
convert_code_addr_to_desc_addr (word, &desc);
word = desc;
}
if (greg <= 10)
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum +
greg, word);
write_memory_unsigned_integer (gparam, tdep->wordsize,
word);
}
greg++;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else
{
int byte;
for (byte = 0; byte < TYPE_LENGTH (type);
byte += tdep->wordsize)
{
if (write_pass && greg <= 10)
{
gdb_byte regval[MAX_REGISTER_SIZE];
int len = TYPE_LENGTH (type) - byte;
if (len > tdep->wordsize)
len = tdep->wordsize;
memset (regval, 0, sizeof regval);
/* WARNING: cagney/2003-09-21: As best I can
tell, the ABI specifies that the value should
be left aligned. Unfortunately, GCC doesn't
do this - it instead right aligns even sized
values and puts odd sized values on the
stack. Work around that by putting both a
left and right aligned value into the
register (hopefully no one notices :-^).
Arrrgh! */
/* Left aligned (8 byte values such as pointers
fill the buffer). */
memcpy (regval, val + byte, len);
/* Right aligned (but only if even). */
if (len == 1 || len == 2 || len == 4)
memcpy (regval + tdep->wordsize - len,
val + byte, len);
regcache_cooked_write (regcache, greg, regval);
}
greg++;
}
if (write_pass)
/* WARNING: cagney/2003-09-21: Strictly speaking, this
isn't necessary, unfortunately, GCC appears to get
"struct convention" parameter passing wrong putting
odd sized structures in memory instead of in a
register. Work around this by always writing the
value to memory. Fortunately, doing this
simplifies the code. */
write_memory (gparam, val, TYPE_LENGTH (type));
if (write_pass)
/* WARNING: cagney/2004-06-20: It appears that GCC
likes to put structures containing a single
floating-point member in an FP register instead of
general general purpose. */
/* Always consume parameter stack space. */
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
}
if (!write_pass)
{
/* Save the true region sizes ready for the second pass. */
vparam_size = vparam;
/* Make certain that the general parameter save area is at
least the minimum 8 registers (or doublewords) in size. */
if (greg < 8)
gparam_size = 8 * tdep->wordsize;
else
gparam_size = gparam;
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, back_chain);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
/* Use the func_addr to find the descriptor, and use that to find
the TOC. */
{
CORE_ADDR desc_addr;
if (convert_code_addr_to_desc_addr (func_addr, &desc_addr))
{
/* The TOC is the second double word in the descriptor. */
CORE_ADDR toc =
read_memory_unsigned_integer (desc_addr + tdep->wordsize,
tdep->wordsize);
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum + 2, toc);
}
}
return sp;
}
static CORE_ADDR
m88k_store_arguments (struct regcache *regcache, int nargs,
struct value **args, CORE_ADDR sp)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int num_register_words = 0;
int num_stack_words = 0;
int i;
for (i = 0; i < nargs; i++)
{
struct type *type = value_type (args[i]);
int len = TYPE_LENGTH (type);
if (m88k_integral_or_pointer_p (type) && len < 4)
{
args[i] = value_cast (builtin_type (gdbarch)->builtin_int32,
args[i]);
type = value_type (args[i]);
len = TYPE_LENGTH (type);
}
if (m88k_in_register_p (type))
{
int num_words = 0;
if (num_register_words % 2 == 1 && m88k_8_byte_align_p (type))
num_words++;
num_words += ((len + 3) / 4);
if (num_register_words + num_words <= 8)
{
num_register_words += num_words;
continue;
}
/* We've run out of available registers. Pass the argument
on the stack. */
}
if (num_stack_words % 2 == 1 && m88k_8_byte_align_p (type))
num_stack_words++;
num_stack_words += ((len + 3) / 4);
}
/* Allocate stack space. */
sp = align_down (sp - 32 - num_stack_words * 4, 16);
num_stack_words = num_register_words = 0;
for (i = 0; i < nargs; i++)
{
const bfd_byte *valbuf = value_contents (args[i]);
struct type *type = value_type (args[i]);
int len = TYPE_LENGTH (type);
int stack_word = num_stack_words;
if (m88k_in_register_p (type))
{
int register_word = num_register_words;
if (register_word % 2 == 1 && m88k_8_byte_align_p (type))
register_word++;
gdb_assert (len == 4 || len == 8);
if (register_word + len / 8 < 8)
{
int regnum = M88K_R2_REGNUM + register_word;
regcache_raw_write (regcache, regnum, valbuf);
if (len > 4)
regcache_raw_write (regcache, regnum + 1, valbuf + 4);
num_register_words = (register_word + len / 4);
continue;
}
}
if (stack_word % 2 == -1 && m88k_8_byte_align_p (type))
stack_word++;
write_memory (sp + stack_word * 4, valbuf, len);
num_stack_words = (stack_word + (len + 3) / 4);
}
return sp;
}
template <typename T, typename S> constexpr T align_up(T val, S alignment) {
return align_down(val + alignment - 1, alignment);
}
static CORE_ADDR
i386_darwin_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[4];
int i;
int write_pass;
/* Determine the total space required for arguments and struct
return address in a first pass, then push arguments in a second pass. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int args_space = 0;
int num_m128 = 0;
if (struct_return)
{
if (write_pass)
{
/* Push value address. */
store_unsigned_integer (buf, 4, byte_order, struct_addr);
write_memory (sp, buf, 4);
}
args_space += 4;
}
for (i = 0; i < nargs; i++)
{
struct type *arg_type = value_enclosing_type (args[i]);
if (i386_m128_p (arg_type) && num_m128 < 4)
{
if (write_pass)
{
const gdb_byte *val = value_contents_all (args[i]);
regcache_raw_write
(regcache, I387_MM0_REGNUM(tdep) + num_m128, val);
}
num_m128++;
}
else
{
args_space = align_up (args_space,
i386_darwin_arg_type_alignment (arg_type));
if (write_pass)
write_memory (sp + args_space,
value_contents_all (args[i]),
TYPE_LENGTH (arg_type));
/* The System V ABI says that:
"An argument's size is increased, if necessary, to make it a
multiple of [32-bit] words. This may require tail padding,
depending on the size of the argument."
This makes sure the stack stays word-aligned. */
args_space += align_up (TYPE_LENGTH (arg_type), 4);
}
}
/* Darwin i386 ABI:
1. The caller ensures that the stack is 16-byte aligned at the point
of the function call. */
if (!write_pass)
sp = align_down (sp - args_space, 16);
}
/* Store return address. */
sp -= 4;
store_unsigned_integer (buf, 4, byte_order, bp_addr);
write_memory (sp, buf, 4);
/* Finally, update the stack pointer... */
store_unsigned_integer (buf, 4, byte_order, sp);
regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
/* ...and fake a frame pointer. */
regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
/* MarkK wrote: This "+ 8" is all over the place:
(i386_frame_this_id, i386_sigtramp_frame_this_id,
i386_dummy_id). It's there, since all frame unwinders for
a given target have to agree (within a certain margin) on the
definition of the stack address of a frame. Otherwise frame id
comparison might not work correctly. Since DWARF2/GCC uses the
stack address *before* the function call as a frame's CFA. On
the i386, when %ebp is used as a frame pointer, the offset
between the contents %ebp and the CFA as defined by GCC. */
return sp + 8;
}
template <class T, typename S> T *align_down(T *ptr, S alignment) {
auto val = reinterpret_cast<uintptr_t>(ptr);
return reinterpret_cast<T *>(align_down(val, alignment));
}
CORE_ADDR
ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
const CORE_ADDR saved_sp = read_sp ();
int argspace = 0; /* 0 is an initial wrong guess. */
int write_pass;
/* Go through the argument list twice.
Pass 1: Figure out how much new stack space is required for
arguments and pushed values. Unlike the PowerOpen ABI, the SysV
ABI doesn't reserve any extra space for parameters which are put
in registers, but does always push structures and then pass their
address.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-float, non-vector
arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* Arguments start above the "LR save word" and "Back chain". */
int argoffset = 2 * tdep->wordsize;
/* Structures start after the arguments. */
int structoffset = argoffset + argspace;
/* If the function is returning a `struct', then the first word
(which will be passed in r3) is used for struct return
address. In that case we should advance one word and start
from r4 register to copy parameters. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (VALUE_TYPE (arg));
int len = TYPE_LENGTH (type);
char *val = VALUE_CONTENTS (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT
&& ppc_floating_point_unit_p (current_gdbarch) && len <= 8)
{
/* Floating point value converted to "double" then
passed in an FP register, when the registers run out,
8 byte aligned stack is used. */
if (freg <= 8)
{
if (write_pass)
{
/* Always store the floating point value using
the register's floating-point format. */
char regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum + freg);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
freg++;
}
else
{
/* SysV ABI converts floats to doubles before
writing them to an 8 byte aligned stack location. */
argoffset = align_up (argoffset, 8);
if (write_pass)
{
char memval[8];
struct type *memtype;
switch (TARGET_BYTE_ORDER)
{
case BFD_ENDIAN_BIG:
memtype = builtin_type_ieee_double_big;
break;
case BFD_ENDIAN_LITTLE:
memtype = builtin_type_ieee_double_little;
break;
default:
internal_error (__FILE__, __LINE__, "bad switch");
}
convert_typed_floating (val, type, memval, memtype);
write_memory (sp + argoffset, val, len);
}
argoffset += 8;
}
}
else if (len == 8 && (TYPE_CODE (type) == TYPE_CODE_INT /* long long */
|| (!ppc_floating_point_unit_p (current_gdbarch) && TYPE_CODE (type) == TYPE_CODE_FLT))) /* double */
{
/* "long long" or "double" passed in an odd/even
register pair with the low addressed word in the odd
register and the high addressed word in the even
register, or when the registers run out an 8 byte
aligned stack location. */
if (greg > 9)
{
/* Just in case GREG was 10. */
greg = 11;
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += 8;
}
else if (tdep->wordsize == 8)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg, val);
greg += 1;
}
else
{
/* Must start on an odd register - r3/r4 etc. */
if ((greg & 1) == 0)
greg++;
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 0,
val + 0);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 4);
}
greg += 2;
}
}
else if (len == 16
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type) && tdep->ppc_vr0_regnum >= 0)
{
/* Vector parameter passed in an Altivec register, or
when that runs out, 16 byte aligned stack location. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (current_regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
argoffset = align_up (argoffset, 16);
if (write_pass)
write_memory (sp + argoffset, val, 16);
argoffset += 16;
}
}
else if (len == 8
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type) && tdep->ppc_ev0_regnum >= 0)
{
/* Vector parameter passed in an e500 register, or when
that runs out, 8 byte aligned stack location. Note
that since e500 vector and general purpose registers
both map onto the same underlying register set, a
"greg" and not a "vreg" is consumed here. A cooked
write stores the value in the correct locations
within the raw register cache. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (current_regcache,
tdep->ppc_ev0_regnum + greg, val);
greg++;
}
else
{
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, 8);
argoffset += 8;
}
}
else
{
/* Reduce the parameter down to something that fits in a
"word". */
char word[MAX_REGISTER_SIZE];
memset (word, 0, MAX_REGISTER_SIZE);
if (len > tdep->wordsize
|| TYPE_CODE (type) == TYPE_CODE_STRUCT
|| TYPE_CODE (type) == TYPE_CODE_UNION)
{
/* Structs and large values are put on an 8 byte
aligned stack ... */
structoffset = align_up (structoffset, 8);
if (write_pass)
write_memory (sp + structoffset, val, len);
/* ... and then a "word" pointing to that address is
passed as the parameter. */
store_unsigned_integer (word, tdep->wordsize,
sp + structoffset);
structoffset += len;
}
else if (TYPE_CODE (type) == TYPE_CODE_INT)
/* Sign or zero extend the "int" into a "word". */
store_unsigned_integer (word, tdep->wordsize,
unpack_long (type, val));
else
/* Always goes in the low address. */
memcpy (word, val, len);
/* Store that "word" in a register, or on the stack.
The words have "4" byte alignment. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg, word);
greg++;
}
else
{
argoffset = align_up (argoffset, tdep->wordsize);
if (write_pass)
write_memory (sp + argoffset, word, tdep->wordsize);
argoffset += tdep->wordsize;
}
}
}
/* Compute the actual stack space requirements. */
if (!write_pass)
{
/* Remember the amount of space needed by the arguments. */
argspace = argoffset;
/* Allocate space for both the arguments and the structures. */
sp -= (argoffset + structoffset);
/* Ensure that the stack is still 16 byte aligned. */
sp = align_down (sp, 16);
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, saved_sp);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
return sp;
}
