void
_dec_2100_a500_init(void)
{
switch (cputype) {
case ST_DEC_2100_A500:
if (alpha_implver() == ALPHA_IMPLVER_EV5)
platform.family = "AlphaServer 2100 (\"Sable-Gamma\")";
else
platform.family = "AlphaServer 2100 (\"Sable\")";
break;
case ST_DEC_2100A_A500:
platform.family = "AlphaServer 2100A (\"Lynx\")";
break;
default:
panic("dec_2100_a500_init: Not a Sable, Sable-Gamma, or Lynx?");
}
if ((platform.model = alpha_dsr_sysname()) == NULL) {
/* XXX don't know variations yet */
platform.model = alpha_unknown_sysname();
}
platform.iobus = "ttwoga";
platform.cons_init = dec_2100_a500_cons_init;
platform.device_register = dec_2100_a500_device_register;
platform.mcheck_handler = dec_2100_a500_machine_check;
}
void
dec_2100_a500_init(cputype)
{
/*
* See if we're a `Sable' or a `Lynx'.
*/
if (cputype == ST_DEC_2100_A500) {
if (alpha_implver() == ALPHA_IMPLVER_EV5)
sable_lynx_base = LYNX_BASE;
else
sable_lynx_base = SABLE_BASE;
platform.family = "DEC AlphaServer 2100";
} else if (cputype == ST_DEC_2100A_A500) {
sable_lynx_base = LYNX_BASE;
platform.family = "DEC AlphaServer 2100A";
} else {
sable_lynx_base = SABLE_BASE;
platform.family = "DEC AlphaServer 2100?????";
}
if ((platform.model = alpha_dsr_sysname()) == NULL) {
platform.model = alpha_unknown_sysname();
}
platform.iobus = "t2";
platform.cons_init = dec_2100_a500_cons_init;
platform.pci_intr_init = dec_2100_a500_intr_init;
t2_init();
}
void
ttwoga_dma_init(struct ttwoga_config *tcp)
{
bus_dma_tag_t t;
/*
* Initialize the DMA tag used for direct-mapped DMA.
*/
t = &tcp->tc_dmat_direct;
t->_cookie = tcp;
t->_wbase = TTWOGA_DIRECT_MAPPED_BASE;
t->_wsize = TTWOGA_DIRECT_MAPPED_SIZE;
t->_next_window = NULL;
t->_boundary = 0;
t->_sgmap = NULL;
t->_get_tag = ttwoga_dma_get_tag;
t->_dmamap_create = _bus_dmamap_create;
t->_dmamap_destroy = _bus_dmamap_destroy;
t->_dmamap_load = _bus_dmamap_load_direct;
t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct;
t->_dmamap_load_uio = _bus_dmamap_load_uio_direct;
t->_dmamap_load_raw = _bus_dmamap_load_raw_direct;
t->_dmamap_unload = _bus_dmamap_unload;
t->_dmamap_sync = _bus_dmamap_sync;
t->_dmamem_alloc = _bus_dmamem_alloc;
t->_dmamem_free = _bus_dmamem_free;
t->_dmamem_map = _bus_dmamem_map;
t->_dmamem_unmap = _bus_dmamem_unmap;
t->_dmamem_mmap = _bus_dmamem_mmap;
/*
* Initialize the DMA tag used for sgmap-mapped DMA.
*/
t = &tcp->tc_dmat_sgmap;
t->_cookie = tcp;
t->_wbase = TTWOGA_SGMAP_MAPPED_BASE;
t->_wsize = TTWOGA_SGMAP_MAPPED_SIZE;
t->_next_window = NULL;
t->_boundary = 0;
t->_sgmap = &tcp->tc_sgmap;
t->_pfthresh = TTWOGA_SGMAP_PFTHRESH;
t->_get_tag = ttwoga_dma_get_tag;
t->_dmamap_create = alpha_sgmap_dmamap_create;
t->_dmamap_destroy = alpha_sgmap_dmamap_destroy;
t->_dmamap_load = ttwoga_bus_dmamap_load_sgmap;
t->_dmamap_load_mbuf = ttwoga_bus_dmamap_load_mbuf_sgmap;
t->_dmamap_load_uio = ttwoga_bus_dmamap_load_uio_sgmap;
t->_dmamap_load_raw = ttwoga_bus_dmamap_load_raw_sgmap;
t->_dmamap_unload = ttwoga_bus_dmamap_unload_sgmap;
t->_dmamap_sync = _bus_dmamap_sync;
t->_dmamem_alloc = _bus_dmamem_alloc;
t->_dmamem_free = _bus_dmamem_free;
t->_dmamem_map = _bus_dmamem_map;
t->_dmamem_unmap = _bus_dmamem_unmap;
t->_dmamem_mmap = _bus_dmamem_mmap;
/*
* Disable the SGMAP TLB, and flush it. We reenable it if
* we have a Sable or a Gamma with T3 or T4; Gamma with T2
* has a TLB bug apparently severe enough to require disabling
* it.
*/
alpha_mb();
T2GA(tcp, T2_IOCSR) &= ~IOCSR_ETLB;
alpha_mb();
alpha_mb(); /* MAGIC */
TTWOGA_TLB_INVALIDATE(tcp);
/*
* XXX We might want to make sure our DMA windows don't
* XXX overlap with PCI memory space!
*/
/*
* Set up window 1 as a 1G direct-mapped window
* starting at 1G.
*/
T2GA(tcp, T2_WBASE1) = 0;
alpha_mb();
T2GA(tcp, T2_WMASK1) = (TTWOGA_DIRECT_MAPPED_SIZE - 1) & WMASKx_PWM;
alpha_mb();
T2GA(tcp, T2_TBASE1) = 0;
alpha_mb();
T2GA(tcp, T2_WBASE1) = TTWOGA_DIRECT_MAPPED_BASE |
((TTWOGA_DIRECT_MAPPED_BASE + (TTWOGA_DIRECT_MAPPED_SIZE - 1)) >>
WBASEx_PWxA_SHIFT) | WBASEx_PWE;
alpha_mb();
/*
* Initialize the SGMAP.
*/
alpha_sgmap_init(t, &tcp->tc_sgmap, "ttwoga_sgmap",
TTWOGA_SGMAP_MAPPED_BASE, 0, TTWOGA_SGMAP_MAPPED_SIZE,
sizeof(u_int64_t), NULL, 0);
/*
* Set up window 2 as an 8MB SGMAP-mapped window
* starting at 8MB.
*/
#ifdef DIAGNOSTIC
if ((TTWOGA_SGMAP_MAPPED_BASE & WBASEx_PWSA) !=
TTWOGA_SGMAP_MAPPED_BASE)
panic("ttwoga_dma_init: SGMAP base inconsistency");
#endif
T2GA(tcp, T2_WBASE2) = 0;
alpha_mb();
T2GA(tcp, T2_WMASK2) = (TTWOGA_SGMAP_MAPPED_SIZE - 1) & WMASKx_PWM;
alpha_mb();
T2GA(tcp, T2_TBASE2) = tcp->tc_sgmap.aps_ptpa >> 1;
alpha_mb();
T2GA(tcp, T2_WBASE2) = TTWOGA_SGMAP_MAPPED_BASE |
((TTWOGA_SGMAP_MAPPED_BASE + (TTWOGA_SGMAP_MAPPED_SIZE - 1)) >>
WBASEx_PWxA_SHIFT) | WBASEx_SGE | WBASEx_PWE;
alpha_mb();
/*
* Enable SGMAP TLB on Sable or Gamma with T3 or T4; see above.
*/
if (alpha_implver() == ALPHA_IMPLVER_EV4 ||
tcp->tc_rev >= TRN_T3) {
alpha_mb();
T2GA(tcp, T2_IOCSR) |= IOCSR_ETLB;
alpha_mb();
alpha_mb(); /* MAGIC */
tcp->tc_use_tlb = 1;
}
/* XXX XXX BEGIN XXX XXX */
{ /* XXX */
extern paddr_t alpha_XXX_dmamap_or; /* XXX */
alpha_XXX_dmamap_or = TTWOGA_DIRECT_MAPPED_BASE;/* XXX */
} /* XXX */
/* XXX XXX END XXX XXX */
}
