/*
* Flush the TSP scatter/gather TLB.
*/
void
tsp_tlb_invalidate(struct tsp_config *pcp)
{
alpha_mb();
*pcp->pc_tlbia = 0;
alpha_mb();
}
void
irongate_conf_write(void *ipv, pcitag_t tag, int offset, pcireg_t data)
{
int s;
PCI_CONF_LOCK(s);
REGVAL(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff));
alpha_mb();
REGVAL(PCI_CONF_DATA) = data;
alpha_mb();
REGVAL(PCI_CONF_ADDR) = 0;
alpha_mb();
PCI_CONF_UNLOCK(s);
}
static u_int32_t
apecs_swiz_readl(u_int32_t pa)
{
alpha_mb();
apecs_swiz_set_hae_mem(&pa);
return SPARSE_READ_LONG(KV(APECS_PCI_SPARSE), pa);
}
pcireg_t
irongate_conf_read0(void *ipv, pcitag_t tag, int offset)
{
pcireg_t data;
int s;
PCI_CONF_LOCK(s);
REGVAL(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff));
alpha_mb();
data = REGVAL(PCI_CONF_DATA);
REGVAL(PCI_CONF_ADDR) = 0;
alpha_mb();
PCI_CONF_UNLOCK(s);
return (data);
}
void
alpha_ipi_pause(struct cpu_info *ci, struct trapframe *framep)
{
u_long cpumask = (1UL << ci->ci_cpuid);
int s;
s = splhigh();
/* Point debuggers at our trapframe for register state. */
ci->ci_db_regs = framep;
atomic_setbits_ulong(&ci->ci_flags, CPUF_PAUSED);
/* Spin with interrupts disabled until we're resumed. */
do {
alpha_mb();
} while (cpus_paused & cpumask);
atomic_clearbits_ulong(&ci->ci_flags, CPUF_PAUSED);
ci->ci_db_regs = NULL;
splx(s);
/* Do an IMB on the way out, in case the kernel text was changed. */
alpha_pal_imb();
}
void
__mp_lock(struct __mp_lock *mpl)
{
int s;
struct cpu_info *ci = curcpu();
/*
* Please notice that mpl_count gets incremented twice for the
* first lock. This is on purpose. The way we release the lock
* in mp_unlock is to decrement the mpl_count and then check if
* the lock should be released. Since mpl_count is what we're
* spinning on, decrementing it in mpl_unlock to 0 means that
* we can't clear mpl_cpu, because we're no longer holding the
* lock. In theory mpl_cpu doesn't need to be cleared, but it's
* safer to clear it and besides, setting mpl_count to 2 on the
* first lock makes most of this code much simpler.
*/
while (1) {
s = splhigh();
if (__cpu_cas(&mpl->mpl_count, 0, 1) == 0) {
alpha_mb();
mpl->mpl_cpu = ci;
}
if (mpl->mpl_cpu == ci) {
mpl->mpl_count++;
splx(s);
break;
}
splx(s);
__mp_lock_spin(mpl);
}
}
void
tsp_bus_mem_init2(bus_space_tag_t t, void *v)
{
struct tsp_config *pcp = v;
struct ts_pchip *pccsr = pcp->pc_csr;
int i, error;
/*
* Allocate the DMA windows out of the extent map.
*/
for (i = 0; i < 4; i++) {
alpha_mb();
if ((pccsr->tsp_wsba[i].tsg_r & WSBA_ENA) == 0) {
/* Window not in use. */
continue;
}
error = extent_alloc_region(CHIP_MEM_EXTENT(v),
WSBA_ADDR(pccsr->tsp_wsba[i].tsg_r),
WSM_LEN(pccsr->tsp_wsm[i].tsg_r),
EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
if (error) {
printf("WARNING: unable to reserve DMA window "
"0x%lx - 0x%lx\n",
WSBA_ADDR(pccsr->tsp_wsba[i].tsg_r),
WSBA_ADDR(pccsr->tsp_wsba[i].tsg_r) +
(WSM_LEN(pccsr->tsp_wsm[i].tsg_r) - 1));
}
}
}
void
alpha_pci_io_swiz_outl(bus_addr_t ioaddr, uint32_t val)
{
uint32_t *port = alpha_pci_io_swiz(ioaddr, 3);
*port = val;
alpha_mb();
}
void
ttwoga_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
{
struct ttwoga_config *tcp = cpv;
pcireg_t *datap;
int b, d, f;
paddr_t addr;
uint64_t old_hae3;
if ((unsigned int)offset >= PCI_CONF_SIZE)
return;
pci_decompose_tag(&tcp->tc_pc, tag, &b, &d, &f);
addr = b ? tag : ttwoga_make_type0addr(d, f);
if (addr == (paddr_t)-1)
return;
TTWOGA_CONF_LOCK();
alpha_mb();
old_hae3 = T2GA(tcp, T2_HAE0_3) & ~HAE0_3_PCA;
T2GA(tcp, T2_HAE0_3) =
old_hae3 | ((b ? 1UL : 0UL) << HAE0_3_PCA_SHIFT);
alpha_mb();
alpha_mb();
datap =
(pcireg_t *)ALPHA_PHYS_TO_K0SEG(tcp->tc_sysmap->tsmap_conf_base |
addr << 5UL | /* address shift */
(offset & ~0x03) << 5UL | /* address shift */
0x3 << 3UL); /* 4-byte, size shift */
alpha_mb();
*datap = data;
alpha_mb();
alpha_mb();
alpha_mb();
T2GA(tcp, T2_HAE0_3) = old_hae3;
alpha_mb();
alpha_mb();
TTWOGA_CONF_UNLOCK();
#if 0
printf("ttwoga_conf_write: tag 0x%lx, reg 0x%x -> 0x%x @ %p\n",
tag, offset, data, datap);
#endif
}
uint32_t
alpha_pci_io_swiz_inl(bus_addr_t ioaddr)
{
uint32_t *port = alpha_pci_io_swiz(ioaddr, 3);
alpha_mb();
return (*port);
}
static u_int32_t
apecs_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r)
{
struct apecs_softc* sc = APECS_SOFTC(apecs0);
vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
alpha_mb();
if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return ~0;
return SPARSE_READ_LONG(sc->cfg0_base, off);
}
pcireg_t
ttwoga_conf_read(void *cpv, pcitag_t tag, int offset)
{
struct ttwoga_config *tcp = cpv;
pcireg_t *datap, data;
int b, d, f, ba;
paddr_t addr;
uint64_t old_hae3;
if ((unsigned int)offset >= PCI_CONF_SIZE)
return (pcireg_t) -1;
pci_decompose_tag(&tcp->tc_pc, tag, &b, &d, &f);
addr = b ? tag : ttwoga_make_type0addr(d, f);
if (addr == (paddr_t)-1)
return ((pcireg_t) -1);
TTWOGA_CONF_LOCK();
alpha_mb();
old_hae3 = T2GA(tcp, T2_HAE0_3) & ~HAE0_3_PCA;
T2GA(tcp, T2_HAE0_3) =
old_hae3 | ((b ? 1UL : 0UL) << HAE0_3_PCA_SHIFT);
alpha_mb();
alpha_mb();
datap =
(pcireg_t *)ALPHA_PHYS_TO_K0SEG(tcp->tc_sysmap->tsmap_conf_base |
addr << 5UL | /* address shift */
(offset & ~0x03) << 5UL | /* address shift */
0x3 << 3UL); /* 4-byte, size shift */
data = (pcireg_t)-1;
if (!(ba = badaddr(datap, sizeof *datap)))
data = *datap;
alpha_mb();
T2GA(tcp, T2_HAE0_3) = old_hae3;
alpha_mb();
alpha_mb();
alpha_pal_draina();
alpha_mb();
alpha_mb();
TTWOGA_CONF_UNLOCK();
#if 0
printf("ttwoga_conf_read: tag 0x%lx, reg 0x%x -> 0x%x @ %p%s\n",
tag, offset, data, datap, ba ? " (badaddr)" : "");
#endif
return (data);
}
void
alpha_pci_io_swiz_outw(bus_addr_t ioaddr, uint16_t val)
{
uint32_t *port = alpha_pci_io_swiz(ioaddr, 1);
bus_addr_t offset = ioaddr & 3;
uint32_t nval = ((uint32_t)val) << (uint32_t)(8 * offset);
*port = nval;
alpha_mb();
}
inline u_int8_t
jensenio_intio_read_1(void *v, bus_space_handle_t ioh, bus_size_t off)
{
register u_int32_t *port;
alpha_mb();
port = (u_int32_t *)(ioh + (off << 9));
return (*port & 0xff);
}
uint16_t
alpha_pci_io_swiz_inw(bus_addr_t ioaddr)
{
uint32_t *port = alpha_pci_io_swiz(ioaddr, 1);
bus_addr_t offset = ioaddr & 3;
alpha_mb();
return ((*port >> (8 * offset)) & 0xffff);
}
inline void
jensenio_intio_barrier(void *v, bus_space_handle_t h, bus_size_t o,
bus_size_t l, int f)
{
if ((f & BUS_SPACE_BARRIER_READ) != 0)
alpha_mb();
else if ((f & BUS_SPACE_BARRIER_WRITE) != 0)
alpha_wmb();
}
void
alpha_pci_io_bwx_outb(bus_addr_t ioaddr, uint8_t val)
{
struct alpha_bus_window *abw = alpha_pci_io_findwindow(ioaddr);
uint8_t *port = (uint8_t *) ((char *)abw->abw_addr +
(ioaddr - abw->abw_abst.abst_bus_start));
alpha_stb(port, val);
alpha_mb();
}
inline void
jensenio_intio_write_1(void *v, bus_space_handle_t ioh, bus_size_t off,
u_int8_t val)
{
register u_int32_t *port;
port = (u_int32_t *)(ioh + (off << 9));
*port = val;
alpha_mb();
}
uint8_t
alpha_pci_io_bwx_inb(bus_addr_t ioaddr)
{
struct alpha_bus_window *abw = alpha_pci_io_findwindow(ioaddr);
uint8_t *port = (uint8_t *) ((char *)abw->abw_addr +
(ioaddr - abw->abw_abst.abst_bus_start));
alpha_mb();
return (alpha_ldbu(port));
}
void
alpha_pci_io_bwx_outl(bus_addr_t ioaddr, uint32_t val)
{
struct alpha_bus_window *abw = alpha_pci_io_findwindow(ioaddr);
/* LINTED */
uint32_t *port = (uint32_t *) ((char *)abw->abw_addr +
(ioaddr - abw->abw_abst.abst_bus_start));
*port = val;
alpha_mb();
}
uint32_t
alpha_pci_io_bwx_inl(bus_addr_t ioaddr)
{
struct alpha_bus_window *abw = alpha_pci_io_findwindow(ioaddr);
/* LINTED */
uint32_t *port = (uint32_t *) ((char *)abw->abw_addr +
(ioaddr - abw->abw_abst.abst_bus_start));
alpha_mb();
return (*port);
}
static inline void
__C(CHIP,_mem_write_8)(
void *v,
bus_space_handle_t memh,
bus_size_t off,
uint64_t val)
{
/* XXX XXX XXX */
panic("%s not implemented", __S(__C(CHIP,_mem_write_8)));
alpha_mb();
}
static inline uint64_t
__C(CHIP,_mem_read_8)(
void *v,
bus_space_handle_t memh,
bus_size_t off)
{
alpha_mb();
/* XXX XXX XXX */
panic("%s not implemented", __S(__C(CHIP,_mem_read_8)));
}
static inline uint8_t
__C(CHIP,_mem_read_1)(
void *v,
bus_space_handle_t memh,
bus_size_t off)
{
bus_addr_t addr;
addr = memh + off;
alpha_mb();
return (alpha_ldbu((uint8_t *)addr));
}
void
cia_pyxis_intr_enable(int irq, int onoff)
{
uint64_t imask;
int s;
#if 0
printf("cia_pyxis_intr_enable: %s %d\n",
onoff ? "enabling" : "disabling", irq);
#endif
s = splhigh();
alpha_mb();
imask = REGVAL64(PYXIS_INT_MASK);
if (onoff)
imask |= (1UL << irq);
else
imask &= ~(1UL << irq);
REGVAL64(PYXIS_INT_MASK) = imask;
alpha_mb();
splx(s);
}
static inline void
__C(CHIP,_mem_write_1)(
void *v,
bus_space_handle_t memh,
bus_size_t off,
uint8_t val)
{
bus_addr_t addr;
addr = memh + off;
alpha_stb((uint8_t *)addr, val);
alpha_mb();
}
static inline void
__C(CHIP,_mem_barrier)(
void *v,
bus_space_handle_t h,
bus_size_t o,
bus_size_t l,
int f)
{
if ((f & BUS_SPACE_BARRIER_READ) != 0)
alpha_mb();
else if ((f & BUS_SPACE_BARRIER_WRITE) != 0)
alpha_wmb();
}
static inline uint32_t
__C(CHIP,_mem_read_4)(
void *v,
bus_space_handle_t memh,
bus_size_t off)
{
bus_addr_t addr;
addr = memh + off;
#ifdef DIAGNOSTIC
if (addr & 3)
panic(__S(__C(CHIP,_mem_read_4)) ": addr 0x%lx not aligned",
addr);
#endif
alpha_mb();
return (*(uint32_t *)addr);
}
static __inline void
apecs_swiz_set_hae_mem(u_int32_t *pa)
{
int s;
u_int32_t msb;
if(*pa >= REG1){
msb = *pa & 0xf8000000;
*pa -= msb;
s = splhigh();
if (msb != apecs_hae_mem) {
apecs_hae_mem = msb;
REGVAL(EPIC_HAXR1) = apecs_hae_mem;
alpha_mb();
apecs_hae_mem = REGVAL(EPIC_HAXR1);
}
splx(s);
}
}
static inline void
__C(CHIP,_mem_write_4)(
void *v,
bus_space_handle_t memh,
bus_size_t off,
uint32_t val)
{
bus_addr_t addr;
addr = memh + off;
#ifdef DIAGNOSTIC
if (addr & 3)
panic(__S(__C(CHIP,_mem_write_4)) ": addr 0x%lx not aligned",
addr);
#endif
*(uint32_t *)addr = val;
alpha_mb();
}
