static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain)
{
struct amdgpu_bo_alloc_request req = {0};
amdgpu_bo_handle buf_handle;
amdgpu_va_handle va_handle;
uint64_t va = 0;
int r;
req.alloc_size = ALIGN(size, 4096);
req.preferred_heap = domain;
r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_va_range_alloc(device_handle,
amdgpu_gpu_va_range_general,
req.alloc_size, 1, 0, &va,
&va_handle, 0);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
AMDGPU_VA_OP_MAP);
CU_ASSERT_EQUAL(r, 0);
vce_bo->addr = va;
vce_bo->handle = buf_handle;
vce_bo->size = req.alloc_size;
vce_bo->va_handle = va_handle;
r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr);
CU_ASSERT_EQUAL(r, 0);
memset(vce_bo->ptr, 0, size);
r = amdgpu_bo_cpu_unmap(vce_bo->handle);
CU_ASSERT_EQUAL(r, 0);
}
static void amdgpu_cs_uvd_destroy(void)
{
struct amdgpu_bo_alloc_request req = {0};
amdgpu_bo_handle buf_handle;
amdgpu_va_handle va_handle;
uint64_t va = 0;
void *msg;
int i, r;
req.alloc_size = 4*1024;
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_va_range_alloc(device_handle,
amdgpu_gpu_va_range_general,
req.alloc_size, 1, 0, &va,
&va_handle, 0);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
AMDGPU_VA_OP_MAP);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_cpu_map(buf_handle, &msg);
CU_ASSERT_EQUAL(r, 0);
memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg));
if (family_id >= AMDGPU_FAMILY_VI)
((uint8_t*)msg)[0x10] = 7;
r = amdgpu_bo_cpu_unmap(buf_handle);
CU_ASSERT_EQUAL(r, 0);
num_resources = 0;
resources[num_resources++] = buf_handle;
resources[num_resources++] = ib_handle;
i = 0;
uvd_cmd(va, 0x0, &i);
for (; i % 16; ++i)
ib_cpu[i] = 0x80000000;
r = submit(i, AMDGPU_HW_IP_UVD);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_va_range_free(va_handle);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_free(buf_handle);
CU_ASSERT_EQUAL(r, 0);
}
static void check_result(struct amdgpu_vce_encode *enc)
{
uint64_t sum;
uint32_t s[2] = {180325, 15946};
uint32_t *ptr, size;
int i, j, r;
for (i = 0; i < 2; ++i) {
r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr);
CU_ASSERT_EQUAL(r, 0);
ptr = (uint32_t *)enc->fb[i].ptr;
size = ptr[4] - ptr[9];
r = amdgpu_bo_cpu_unmap(enc->fb[i].handle);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr);
CU_ASSERT_EQUAL(r, 0);
for (j = 0, sum = 0; j < size; ++j)
sum += enc->bs[i].ptr[j];
CU_ASSERT_EQUAL(sum, s[i]);
r = amdgpu_bo_cpu_unmap(enc->bs[i].handle);
CU_ASSERT_EQUAL(r, 0);
}
}
static void amdgpu_bo_map_unmap(void)
{
uint32_t *ptr;
int i, r;
r = amdgpu_bo_cpu_map(buffer_handle, (void **)&ptr);
CU_ASSERT_EQUAL(r, 0);
CU_ASSERT_NOT_EQUAL(ptr, NULL);
for (i = 0; i < (BUFFER_SIZE / 4); ++i)
ptr[i] = 0xdeadbeef;
r = amdgpu_bo_cpu_unmap(buffer_handle);
CU_ASSERT_EQUAL(r, 0);
}
int amdgpu_bo_map(ScrnInfoPtr pScrn, struct amdgpu_buffer *bo)
{
AMDGPUInfoPtr info = AMDGPUPTR(pScrn);
int ret = 0;
if (info->use_glamor)
return 0;
if (bo->flags & AMDGPU_BO_FLAGS_GBM) {
uint32_t handle, stride, height;
union drm_amdgpu_gem_mmap args;
int fd;
void *ptr;
handle = gbm_bo_get_handle(bo->bo.gbm).u32;
stride = gbm_bo_get_stride(bo->bo.gbm);
height = gbm_bo_get_height(bo->bo.gbm);
fd = info->dri2.drm_fd;
memset(&args, 0, sizeof(union drm_amdgpu_gem_mmap));
args.in.handle = handle;
ret = drmCommandWriteRead(fd, DRM_AMDGPU_GEM_MMAP,
&args, sizeof(args));
if (ret) {
ErrorF("Failed to get the mmap offset\n");
return ret;
}
ptr = mmap(NULL, stride * height,
PROT_READ | PROT_WRITE, MAP_SHARED,
fd, args.out.addr_ptr);
if (ptr == NULL) {
ErrorF("Failed to mmap the bo\n");
return -1;
}
bo->cpu_ptr = ptr;
} else
ret = amdgpu_bo_cpu_map(bo->bo.amdgpu, &bo->cpu_ptr);
return ret;
}
static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
{
struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
int r;
struct amdgpu_bo_alloc_request alloc_buffer = {};
amdgpu_bo_handle buf_handle;
ctx->ws = amdgpu_winsys(ws);
ctx->refcount = 1;
r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
FREE(ctx);
return NULL;
}
alloc_buffer.alloc_size = 4 * 1024;
alloc_buffer.phys_alignment = 4 *1024;
alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
amdgpu_cs_ctx_free(ctx->ctx);
FREE(ctx);
return NULL;
}
r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
amdgpu_bo_free(buf_handle);
amdgpu_cs_ctx_free(ctx->ctx);
FREE(ctx);
return NULL;
}
memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
ctx->user_fence_bo = buf_handle;
return (struct radeon_winsys_ctx*)ctx;
}
static void *amdgpu_bo_map(struct radeon_winsys_cs_handle *buf,
struct radeon_winsys_cs *rcs,
enum pipe_transfer_usage usage)
{
struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
int r;
void *cpu = NULL;
/* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
/* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
if (usage & PIPE_TRANSFER_DONTBLOCK) {
if (!(usage & PIPE_TRANSFER_WRITE)) {
/* Mapping for read.
*
* Since we are mapping for read, we don't need to wait
* if the GPU is using the buffer for read too
* (neither one is changing it).
*
* Only check whether the buffer is being used for write. */
if (cs && amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo,
RADEON_USAGE_WRITE)) {
cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC, NULL);
return NULL;
}
if (!amdgpu_bo_wait((struct pb_buffer*)bo, 0,
RADEON_USAGE_WRITE)) {
return NULL;
}
} else {
if (cs && amdgpu_bo_is_referenced_by_cs(cs, bo)) {
cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC, NULL);
return NULL;
}
if (!amdgpu_bo_wait((struct pb_buffer*)bo, 0,
RADEON_USAGE_READWRITE)) {
return NULL;
}
}
} else {
uint64_t time = os_time_get_nano();
if (!(usage & PIPE_TRANSFER_WRITE)) {
/* Mapping for read.
*
* Since we are mapping for read, we don't need to wait
* if the GPU is using the buffer for read too
* (neither one is changing it).
*
* Only check whether the buffer is being used for write. */
if (cs && amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo,
RADEON_USAGE_WRITE)) {
cs->flush_cs(cs->flush_data, 0, NULL);
}
amdgpu_bo_wait((struct pb_buffer*)bo, PIPE_TIMEOUT_INFINITE,
RADEON_USAGE_WRITE);
} else {
/* Mapping for write. */
if (cs && amdgpu_bo_is_referenced_by_cs(cs, bo))
cs->flush_cs(cs->flush_data, 0, NULL);
amdgpu_bo_wait((struct pb_buffer*)bo, PIPE_TIMEOUT_INFINITE,
RADEON_USAGE_READWRITE);
}
bo->rws->buffer_wait_time += os_time_get_nano() - time;
}
}
/* If the buffer is created from user memory, return the user pointer. */
if (bo->user_ptr)
return bo->user_ptr;
r = amdgpu_bo_cpu_map(bo->bo, &cpu);
return r ? NULL : cpu;
}
static void amdgpu_cs_vce_encode(void)
{
uint32_t vbuf_size, bs_size = 0x154000, cpb_size;
int r;
vbuf_size = enc.width * enc.height * 1.5;
cpb_size = vbuf_size * 10;
num_resources = 0;
alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
resources[num_resources++] = enc.fb[0].handle;
alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT);
resources[num_resources++] = enc.fb[1].handle;
alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT);
resources[num_resources++] = enc.bs[0].handle;
alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT);
resources[num_resources++] = enc.bs[1].handle;
alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
resources[num_resources++] = enc.vbuf.handle;
alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
resources[num_resources++] = enc.cpb.handle;
resources[num_resources++] = ib_handle;
r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
CU_ASSERT_EQUAL(r, 0);
memcpy(enc.vbuf.ptr, frame, sizeof(frame));
r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
CU_ASSERT_EQUAL(r, 0);
amdgpu_cs_vce_config();
if (family_id >= AMDGPU_FAMILY_VI) {
vce_taskinfo[3] = 3;
amdgpu_cs_vce_encode_idr(&enc);
amdgpu_cs_vce_encode_p(&enc);
check_result(&enc);
/* two pipes */
vce_encode[16] = 0;
amdgpu_cs_vce_encode_idr(&enc);
amdgpu_cs_vce_encode_p(&enc);
check_result(&enc);
/* two instances */
enc.two_instance = true;
vce_taskinfo[2] = 0x83;
vce_taskinfo[4] = 1;
amdgpu_cs_vce_encode_idr(&enc);
vce_taskinfo[2] = 0xffffffff;
vce_taskinfo[4] = 2;
amdgpu_cs_vce_encode_p(&enc);
check_result(&enc);
} else {
vce_taskinfo[3] = 3;
vce_encode[16] = 0;
amdgpu_cs_vce_encode_idr(&enc);
amdgpu_cs_vce_encode_p(&enc);
check_result(&enc);
}
free_resource(&enc.fb[0]);
free_resource(&enc.fb[1]);
free_resource(&enc.bs[0]);
free_resource(&enc.bs[1]);
free_resource(&enc.vbuf);
free_resource(&enc.cpb);
}
static void amdgpu_cs_uvd_decode(void)
{
const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
struct amdgpu_bo_alloc_request req = {0};
amdgpu_bo_handle buf_handle;
amdgpu_va_handle va_handle;
uint64_t va = 0;
uint64_t sum;
uint8_t *ptr;
int i, r;
req.alloc_size = 4*1024; /* msg */
req.alloc_size += 4*1024; /* fb */
if (family_id >= AMDGPU_FAMILY_VI)
req.alloc_size += 4096; /*it_scaling_table*/
req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
req.alloc_size += ALIGN(dpb_size, 4*1024);
req.alloc_size += ALIGN(dt_size, 4*1024);
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_va_range_alloc(device_handle,
amdgpu_gpu_va_range_general,
req.alloc_size, 1, 0, &va,
&va_handle, 0);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
AMDGPU_VA_OP_MAP);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
CU_ASSERT_EQUAL(r, 0);
memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
if (family_id >= AMDGPU_FAMILY_VI) {
ptr[0x10] = 7;
ptr[0x98] = 0x00;
ptr[0x99] = 0x02;
/* chip polaris10/11 */
if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
/*dpb size */
ptr[0x24] = 0x00;
ptr[0x25] = 0x94;
ptr[0x26] = 0x6B;
ptr[0x27] = 0x00;
/*ctx size */
ptr[0x2C] = 0x00;
ptr[0x2D] = 0xAF;
ptr[0x2E] = 0x50;
ptr[0x2F] = 0x00;
}
}
ptr += 4*1024;
memset(ptr, 0, 4*1024);
if (family_id >= AMDGPU_FAMILY_VI) {
ptr += 4*1024;
memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
}
ptr += 4*1024;
memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
memset(ptr, 0, dpb_size);
ptr += ALIGN(dpb_size, 4*1024);
memset(ptr, 0, dt_size);
num_resources = 0;
resources[num_resources++] = buf_handle;
resources[num_resources++] = ib_handle;
msg_addr = va;
fb_addr = msg_addr + 4*1024;
if (family_id >= AMDGPU_FAMILY_VI) {
it_addr = fb_addr + 4*1024;
bs_addr = it_addr + 4*1024;
} else
bs_addr = fb_addr + 4*1024;
dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
if ((family_id >= AMDGPU_FAMILY_VI) &&
(chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
}
dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
i = 0;
uvd_cmd(msg_addr, 0x0, &i);
uvd_cmd(dpb_addr, 0x1, &i);
uvd_cmd(dt_addr, 0x2, &i);
uvd_cmd(fb_addr, 0x3, &i);
uvd_cmd(bs_addr, 0x100, &i);
if (family_id >= AMDGPU_FAMILY_VI) {
uvd_cmd(it_addr, 0x204, &i);
if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)
uvd_cmd(ctx_addr, 0x206, &i);
}
ib_cpu[i++] = 0x3BC6;
ib_cpu[i++] = 0x1;
for (; i % 16; ++i)
ib_cpu[i] = 0x80000000;
r = submit(i, AMDGPU_HW_IP_UVD);
CU_ASSERT_EQUAL(r, 0);
/* TODO: use a real CRC32 */
for (i = 0, sum = 0; i < dt_size; ++i)
sum += ptr[i];
CU_ASSERT_EQUAL(sum, 0x20345d8);
r = amdgpu_bo_cpu_unmap(buf_handle);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_va_range_free(va_handle);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_free(buf_handle);
CU_ASSERT_EQUAL(r, 0);
}
static void amdgpu_cs_uvd_create(void)
{
struct amdgpu_bo_alloc_request req = {0};
amdgpu_bo_handle buf_handle;
uint64_t va = 0;
amdgpu_va_handle va_handle;
void *msg;
int i, r;
req.alloc_size = 4*1024;
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_va_range_alloc(device_handle,
amdgpu_gpu_va_range_general,
4096, 1, 0, &va,
&va_handle, 0);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_cpu_map(buf_handle, &msg);
CU_ASSERT_EQUAL(r, 0);
memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
if (family_id >= AMDGPU_FAMILY_VI) {
((uint8_t*)msg)[0x10] = 7;
/* chip polaris 10/11 */
if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
/* dpb size */
((uint8_t*)msg)[0x28] = 0x00;
((uint8_t*)msg)[0x29] = 0x94;
((uint8_t*)msg)[0x2A] = 0x6B;
((uint8_t*)msg)[0x2B] = 0x00;
}
}
r = amdgpu_bo_cpu_unmap(buf_handle);
CU_ASSERT_EQUAL(r, 0);
num_resources = 0;
resources[num_resources++] = buf_handle;
resources[num_resources++] = ib_handle;
i = 0;
uvd_cmd(va, 0x0, &i);
for (; i % 16; ++i)
ib_cpu[i] = 0x80000000;
r = submit(i, AMDGPU_HW_IP_UVD);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_va_range_free(va_handle);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_free(buf_handle);
CU_ASSERT_EQUAL(r, 0);
}