static sw_error_t _dess_mib_op_commit(a_uint32_t dev_id, a_uint32_t op) { a_uint32_t mib_busy = 1, i = 0x1000, val; sw_error_t rv; while (mib_busy && --i) { HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY, (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); aos_udelay(5); } if (i == 0) return SW_BUSY; HSL_REG_ENTRY_GET(rv, dev_id, MIB_FUNC, 0, (a_uint8_t *) (&val), sizeof (a_uint32_t)); SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val); SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val); HSL_REG_ENTRY_SET(rv, dev_id, MIB_FUNC, 0, (a_uint8_t *) (&val), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); mib_busy = 1; i = 0x1000; while (mib_busy && --i) { HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY, (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); aos_udelay(5); } if (i == 0) return SW_FAIL; return SW_OK; }
static sw_error_t athena_vlan_commit(a_uint32_t dev_id, a_uint32_t op) { a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val; sw_error_t rv; while (vt_busy && --i) { HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY, (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); aos_udelay(5); } if (i == 0) return SW_BUSY; HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, (a_uint8_t *) (&val), sizeof (a_uint32_t)); SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val); SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val); HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, (a_uint8_t *) (&val), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO, (a_uint8_t *) (&vt_full), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (vt_full) { val = 0x10; HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, (a_uint8_t *) (&val), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (VLAN_LOAD_ENTRY == op) { return SW_FULL; } else if (VLAN_PURGE_ENTRY == op) { return SW_NOT_FOUND; } } return SW_OK; }
static sw_error_t garuda_bist_test(a_uint32_t dev_id) { a_uint32_t entry, data, i; sw_error_t rv; data = 1; i = 0x1000; while (data && --i) { HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); aos_udelay(5); } if (0 == i) { return SW_INIT_ERROR; } entry = 0; SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry); SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry); SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry); SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry); HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); data = 1; i = 0x1000; while (data && --i) { HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); aos_udelay(5); } if (0 == i) { return SW_INIT_ERROR; } SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry); if (data) { SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry); if (!data) { return SW_INIT_ERROR; } SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry); entry = 0; SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry); SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry); HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); } else { return SW_OK; } entry = 0; SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry); SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry); SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry); SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry); HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); data = 1; i = 0x1000; while (data && --i) { HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); aos_udelay(5); } if (0 == i) { return SW_INIT_ERROR; } SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry); if (data) { return SW_INIT_ERROR; } return SW_OK; }
static sw_error_t shiva_fdb_commit(a_uint32_t dev_id, a_uint32_t op) { sw_error_t rv; a_uint32_t busy = 1; a_uint32_t full_vio; a_uint32_t i = 1000; a_uint32_t entry; a_uint32_t hwop = op; while (busy && --i) { HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, (a_uint8_t *) (&busy), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); aos_udelay(5); } if (0 == i) { return SW_BUSY; } HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry); if (ARL_FLUSH_PORT_AND_STATIC == hwop) { hwop = ARL_FLUSH_PORT_UNICAST; SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry); } if (ARL_FLUSH_PORT_NO_STATIC == hwop) { hwop = ARL_FLUSH_PORT_UNICAST; SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry); } SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry); HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); busy = 1; i = 1000; while (busy && --i) { HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, (a_uint8_t *) (&busy), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); aos_udelay(5); } if (0 == i) { return SW_FAIL; } HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO, (a_uint8_t *) (&full_vio), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (full_vio) { /* must clear AT_FULL_VOI bit */ entry = 0x1000; HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (ARL_LOAD_ENTRY == hwop) { return SW_FULL; } else if ((ARL_PURGE_ENTRY == hwop) || (ARL_FLUSH_PORT_UNICAST == hwop)) { return SW_NOT_FOUND; } else { return SW_FAIL; } } return SW_OK; }