/* spurious interrupt handler for SMP */
void
mpspurint(void)
{
apiceoi();
return;
}
/*
* Entered in AP core context, upon traps (system calls go through acsyscall)
* using up->dbgreg means cores MUST be homogeneous.
*
* BUG: We should setup some trapenable() mechanism for the AC,
* so that code like fpu.c could arrange for handlers specific for
* the AC, instead of doint that by hand here.
*
* All interrupts are masked while in the "kernel"
*/
void
actrap(Ureg *u)
{
panic("actrap");
#if 0
char *n;
ACVctl *v;
n = nil;
_pmcupdate(m);
if(m->proc != nil){
m->proc->nactrap++;
m->proc->actime1 = fastticks(nil);
}
if(u->type < nelem(acvctl)){
v = acvctl[u->type];
if(v != nil){
DBG("actrap: cpu%d: %ulld\n", machp()->machno, u->type);
n = v->f(u, v->a);
if(n != nil)
goto Post;
return;
}
}
switch(u->type){
case IdtDF:
print("AC: double fault\n");
dumpregs(u);
ndnr();
case IdtIPI:
m->intr++;
DBG("actrap: cpu%d: IPI\n", machp()->machno);
apiceoi(IdtIPI);
break;
case IdtTIMER:
apiceoi(IdtTIMER);
panic("timer interrupt in an AC");
break;
case IdtPF:
/* this case is here for debug only */
m->pfault++;
DBG("actrap: cpu%d: PF cr2 %#ullx\n", machp()->machno, cr2get());
break;
default:
print("actrap: cpu%d: %ulld\n", machp()->machno, u->type);
}
Post:
m->icc->rc = ICCTRAP;
m->cr2 = cr2get();
memmove(m->proc->dbgreg, u, sizeof *u);
m->icc->note = n;
fpuprocsave(m->proc);
_pmcupdate(m);
mfence();
m->icc->fn = nil;
ready(m->proc);
mwait(&m->icc->fn);
if(m->icc->flushtlb)
acmmuswitch();
if(m->icc->fn != actrapret)
acsched();
DBG("actrap: ret\n");
memmove(u, m->proc->dbgreg, sizeof *u);
if(m->proc)
m->proc->actime += fastticks2us(fastticks(nil) - m->proc->actime1);
#endif
}
